2 * See file CREDITS for list of people who contributed to this
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/global_data.h>
26 #include <asm/mpc8349_pci.h>
29 DECLARE_GLOBAL_DATA_PTR;
33 /* System RAM mapped to PCI space */
34 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
35 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
37 #ifndef CONFIG_PCI_PNP
38 static struct pci_config_table pci_mpc8349emds_config_table[] = {
39 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
40 PCI_IDSEL_NUMBER, PCI_ANY_ID,
41 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
43 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
50 static struct pci_controller pci_hose[] = {
52 #ifndef CONFIG_PCI_PNP
53 config_table:pci_mpc8349emds_config_table,
57 #ifndef CONFIG_PCI_PNP
58 config_table:pci_mpc8349emds_config_table,
63 /**************************************************************************
65 * pib_init() -- initialize the PCA9555PW IO expander on the PIB board
71 u8 val8, orig_i2c_bus;
73 * Assign PIB PMC slot to desired PCI bus
75 /* Switch temporarily to I2C bus #2 */
76 orig_i2c_bus = i2c_get_bus_num();
82 i2c_write(0x23, 0x6, 1, &val8, 1);
83 i2c_write(0x23, 0x7, 1, &val8, 1);
85 i2c_write(0x23, 0x2, 1, &val8, 1);
86 i2c_write(0x23, 0x3, 1, &val8, 1);
89 i2c_write(0x26, 0x6, 1, &val8, 1);
91 i2c_write(0x26, 0x7, 1, &val8, 1);
92 #if defined(PCI_64BIT)
93 val8 = 0xf4; /* PMC2:PCI1/64-bit */
94 #elif defined(PCI_ALL_PCI1)
95 val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
96 #elif defined(PCI_ONE_PCI1)
97 val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
99 val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
101 i2c_write(0x26, 0x2, 1, &val8, 1);
103 i2c_write(0x26, 0x3, 1, &val8, 1);
105 i2c_write(0x27, 0x6, 1, &val8, 1);
106 i2c_write(0x27, 0x7, 1, &val8, 1);
108 i2c_write(0x27, 0x2, 1, &val8, 1);
110 i2c_write(0x27, 0x3, 1, &val8, 1);
113 #if defined(PCI_64BIT)
114 printf("PCI1: 64-bit on PMC2\n");
115 #elif defined(PCI_ALL_PCI1)
116 printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
117 #elif defined(PCI_ONE_PCI1)
118 printf("PCI1: 32-bit on PMC1\n");
119 printf("PCI2: 32-bit on PMC2, PMC3\n");
121 printf("PCI1: 32-bit on PMC1, PMC2\n");
122 printf("PCI2: 32-bit on PMC3\n");
124 /* Reset to original I2C bus */
125 if(orig_i2c_bus != 2)
126 i2c_set_bus_num(orig_i2c_bus);
129 /**************************************************************************
132 * NOTICE: PCI2 is not currently supported
138 volatile immap_t * immr;
139 volatile clk83xx_t * clk;
140 volatile law83xx_t * pci_law;
141 volatile pot83xx_t * pci_pot;
142 volatile pcictrl83xx_t * pci_ctrl;
143 volatile pciconf83xx_t * pci_conf;
147 struct pci_controller * hose;
149 immr = (immap_t *)CFG_IMMRBAR;
150 clk = (clk83xx_t *)&immr->clk;
151 pci_law = immr->sysconf.pcilaw;
152 pci_pot = immr->ios.pot;
153 pci_ctrl = immr->pci_ctrl;
154 pci_conf = immr->pci_conf;
161 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
166 clk->occr = 0xff000000;
170 * Release PCI RST Output signal
176 #ifdef CONFIG_MPC83XX_PCI2
182 /* We need to wait at least a 1sec based on PCI specs */
186 for (i = 0; i < 1000; ++i)
191 * Configure PCI Local Access Windows
193 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
194 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
196 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
197 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
200 * Configure PCI Outbound Translation Windows
203 /* PCI1 mem space - prefetch */
204 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
205 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
206 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
209 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
210 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
211 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
213 /* PCI1 mmio - non-prefetch mem space */
214 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
215 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
216 pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
219 * Configure PCI Inbound Translation Windows
222 /* we need RAM mapped to PCI space for the devices to
223 * access main memory */
224 pci_ctrl[0].pitar1 = 0x0;
225 pci_ctrl[0].pibar1 = 0x0;
226 pci_ctrl[0].piebar1 = 0x0;
227 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
229 hose->first_busno = 0;
230 hose->last_busno = 0xff;
232 /* PCI memory prefetch space */
233 pci_set_region(hose->regions + 0,
237 PCI_REGION_MEM|PCI_REGION_PREFETCH);
239 /* PCI memory space */
240 pci_set_region(hose->regions + 1,
247 pci_set_region(hose->regions + 2,
253 /* System memory space */
254 pci_set_region(hose->regions + 3,
255 CONFIG_PCI_SYS_MEM_BUS,
256 CONFIG_PCI_SYS_MEM_PHYS,
258 PCI_REGION_MEM | PCI_REGION_MEMORY);
260 hose->region_count = 4;
262 pci_setup_indirect(hose,
263 (CFG_IMMRBAR+0x8300),
264 (CFG_IMMRBAR+0x8304));
266 pci_register_hose(hose);
269 * Write to Command register
272 dev = PCI_BDF(hose->first_busno, 0, 0);
273 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
274 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
275 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
278 * Clear non-reserved bits in status register.
280 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
281 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
282 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
284 #ifdef CONFIG_PCI_SCAN_SHOW
285 printf("PCI: Bus Dev VenId DevId Class Int\n");
290 hose->last_busno = pci_hose_scan(hose);
292 #ifdef CONFIG_MPC83XX_PCI2
296 * Configure PCI Outbound Translation Windows
299 /* PCI2 mem space - prefetch */
300 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
301 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
302 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
305 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
306 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
307 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
309 /* PCI2 mmio - non-prefetch mem space */
310 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
311 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
312 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
315 * Configure PCI Inbound Translation Windows
318 /* we need RAM mapped to PCI space for the devices to
319 * access main memory */
320 pci_ctrl[1].pitar1 = 0x0;
321 pci_ctrl[1].pibar1 = 0x0;
322 pci_ctrl[1].piebar1 = 0x0;
323 pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
325 hose->first_busno = pci_hose[0].last_busno + 1;
326 hose->last_busno = 0xff;
328 /* PCI memory prefetch space */
329 pci_set_region(hose->regions + 0,
333 PCI_REGION_MEM|PCI_REGION_PREFETCH);
335 /* PCI memory space */
336 pci_set_region(hose->regions + 1,
343 pci_set_region(hose->regions + 2,
349 /* System memory space */
350 pci_set_region(hose->regions + 3,
351 CONFIG_PCI_SYS_MEM_BUS,
352 CONFIG_PCI_SYS_MEM_PHYS,
354 PCI_REGION_MEM | PCI_REGION_MEMORY);
356 hose->region_count = 4;
358 pci_setup_indirect(hose,
359 (CFG_IMMRBAR+0x8380),
360 (CFG_IMMRBAR+0x8384));
362 pci_register_hose(hose);
365 * Write to Command register
368 dev = PCI_BDF(hose->first_busno, 0, 0);
369 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
370 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
371 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
374 * Clear non-reserved bits in status register.
376 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
377 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
378 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
383 hose->last_busno = pci_hose_scan(hose);
388 #endif /* CONFIG_PCI */