3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/mpc8349_pci.h>
32 #if defined(CONFIG_PCI)
35 #if defined(CONFIG_SPD_EEPROM)
36 #include <spd_sdram.h>
38 int fixed_sdram(void);
39 void sdram_init(void);
41 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
42 void ddr_enable_ecc(unsigned int dram_size);
45 int board_early_init_f (void)
47 volatile u8* bcsr = (volatile u8*)CFG_BCSR;
49 /* Enable flash write */
55 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
57 long int initdram (int board_type)
59 volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
62 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
65 /* DDR SDRAM - Main SODIMM */
66 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
67 #if defined(CONFIG_SPD_EEPROM)
71 msize = fixed_sdram();
74 * Initialize SDRAM if it is on local bus.
78 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
80 * Initialize and enable DDR ECC.
82 ddr_enable_ecc(msize * 1024 * 1024);
85 /* return total bus SDRAM size(bytes) -- DDR */
86 return (msize * 1024 * 1024);
89 #if !defined(CONFIG_SPD_EEPROM)
90 /*************************************************************************
91 * fixed sdram init -- doesn't use serial presence detect.
92 ************************************************************************/
95 volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
100 msize = CFG_DDR_SIZE;
101 for (ddr_size = msize << 20, ddr_size_log2 = 0;
103 ddr_size = ddr_size>>1, ddr_size_log2++) {
108 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
109 #if (CFG_DDR_SIZE != 256)
110 #warning Currenly any ddr size other than 256 is not supported
113 im->ddr.csbnds[0].csbnds = 0x00100017;
114 im->ddr.csbnds[1].csbnds = 0x0018001f;
115 im->ddr.csbnds[2].csbnds = 0x00000007;
116 im->ddr.csbnds[3].csbnds = 0x0008000f;
117 im->ddr.cs_config[0] = CFG_DDR_CONFIG;
118 im->ddr.cs_config[1] = CFG_DDR_CONFIG;
119 im->ddr.cs_config[2] = CFG_DDR_CONFIG;
120 im->ddr.cs_config[3] = CFG_DDR_CONFIG;
121 im->ddr.timing_cfg_1 =
122 3 << TIMING_CFG1_PRETOACT_SHIFT |
123 7 << TIMING_CFG1_ACTTOPRE_SHIFT |
124 3 << TIMING_CFG1_ACTTORW_SHIFT |
125 4 << TIMING_CFG1_CASLAT_SHIFT |
126 3 << TIMING_CFG1_REFREC_SHIFT |
127 3 << TIMING_CFG1_WRREC_SHIFT |
128 2 << TIMING_CFG1_ACTTOACT_SHIFT |
129 1 << TIMING_CFG1_WRTORD_SHIFT;
130 im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
133 #if defined(CONFIG_DDR_2T_TIMING)
136 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
138 0x2000 << SDRAM_MODE_ESD_SHIFT |
139 0x0162 << SDRAM_MODE_SD_SHIFT;
141 im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT |
142 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
145 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
149 #endif/*!CFG_SPD_EEPROM*/
152 int checkboard (void)
154 puts("Board: Freescale MPC8349EMDS\n");
158 #if defined(CONFIG_PCI)
160 * Initialize PCI Devices, report devices found
162 #ifndef CONFIG_PCI_PNP
163 static struct pci_config_table pci_mpc8349emds_config_table[] = {
164 {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
165 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
167 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
173 volatile static struct pci_controller hose[] = {
175 #ifndef CONFIG_PCI_PNP
176 config_table:pci_mpc8349emds_config_table,
180 #ifndef CONFIG_PCI_PNP
181 config_table:pci_mpc8349emds_config_table,
185 #endif /* CONFIG_PCI */
187 void pci_init_board(void)
190 extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
192 pci_mpc83xx_init(hose);
193 #endif /* CONFIG_PCI */
197 * if MPC8349EMDS is soldered with SDRAM
199 #if defined(CFG_BR2_PRELIM) \
200 && defined(CFG_OR2_PRELIM) \
201 && defined(CFG_LBLAWBAR2_PRELIM) \
202 && defined(CFG_LBLAWAR2_PRELIM)
204 * Initialize SDRAM memory on the Local Bus.
207 void sdram_init(void)
209 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
210 volatile lbus8349_t *lbc= &immap->lbus;
211 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
213 puts("\n SDRAM on Local Bus: ");
214 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
217 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
220 /* setup mtrpt, lsrt and lbcr for LB bus */
221 lbc->lbcr = CFG_LBC_LBCR;
222 lbc->mrtpr = CFG_LBC_MRTPR;
223 lbc->lsrt = CFG_LBC_LSRT;
227 * Configure the SDRAM controller Machine Mode Register.
229 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
231 lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
236 lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
263 /* 0x58636733; mode register write operation */
264 lbc->lsdmr = CFG_LBC_LSDMR_4;
269 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
275 void sdram_init(void)
277 put("SDRAM on Local Bus is NOT available!\n");