board/mpc8349emds/mpc8349emds.c

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 #include <common.h>
  26 #include <ioports.h>
  27 #include <mpc83xx.h>
  28 #include <asm/mpc8349_pci.h>
  29 #include <i2c.h>
  30 #include <spd.h>
  31 #include <miiphy.h>
  32 #include <command.h>
  33 #if defined(CONFIG_SPD_EEPROM)
  34 #include <spd_sdram.h>
  35 #endif
  36 #if defined(CONFIG_OF_FLAT_TREE)
  37 #include <ft_build.h>
  38 #endif
  39
  40 int fixed_sdram(void);
  41 void sdram_init(void);
  42
  43 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
  44 void ddr_enable_ecc(unsigned int dram_size);
  45 #endif
  46
  47 int board_early_init_f (void)
  48 {
  49         volatile u8* bcsr = (volatile u8*)CFG_BCSR;
  50
  51         /* Enable flash write */
  52         bcsr[1] &= ~0x01;
  53
  54 #ifdef CFG_USE_MPC834XSYS_USB_PHY
  55         /* Use USB PHY on SYS board */
  56         bcsr[5] |= 0x02;
  57 #endif
  58
  59         return 0;
  60 }
  61
  62 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
  63
  64 long int initdram (int board_type)
  65 {
  66         volatile immap_t *im = (immap_t *)CFG_IMMR;
  67         u32 msize = 0;
  68
  69         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  70                 return -1;
  71
  72         puts("Initializing\n");
  73
  74         /* DDR SDRAM - Main SODIMM */
  75         im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
  76 #if defined(CONFIG_SPD_EEPROM)
  77         msize = spd_sdram();
  78 #else
  79         msize = fixed_sdram();
  80 #endif
  81         /*
  82          * Initialize SDRAM if it is on local bus.
  83          */
  84         sdram_init();
  85
  86 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  87         /*
  88          * Initialize and enable DDR ECC.
  89          */
  90         ddr_enable_ecc(msize * 1024 * 1024);
  91 #endif
  92         puts("   DDR RAM: ");
  93         /* return total bus SDRAM size(bytes)  -- DDR */
  94         return (msize * 1024 * 1024);
  95 }
  96
  97 #if !defined(CONFIG_SPD_EEPROM)
  98 /*************************************************************************
  99  *  fixed sdram init -- doesn't use serial presence detect.
 100  ************************************************************************/
 101 int fixed_sdram(void)
 102 {
 103         volatile immap_t *im = (immap_t *)CFG_IMMR;
 104         u32 msize = 0;
 105         u32 ddr_size;
 106         u32 ddr_size_log2;
 107
 108         msize = CFG_DDR_SIZE;
 109         for (ddr_size = msize << 20, ddr_size_log2 = 0;
 110              (ddr_size > 1);
 111              ddr_size = ddr_size>>1, ddr_size_log2++) {
 112                 if (ddr_size & 1) {
 113                         return -1;
 114                 }
 115         }
 116         im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
 117         im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 118
 119 #if (CFG_DDR_SIZE != 256)
 120 #warning Currenly any ddr size other than 256 is not supported
 121 #endif
 122 #ifdef CONFIG_DDR_II
 123         im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS;
 124         im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG;
 125         im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
 126         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 127         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 128         im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
 129         im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
 130         im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
 131         im->ddr.sdram_mode = CFG_DDR_MODE;
 132         im->ddr.sdram_mode2 = CFG_DDR_MODE2;
 133         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 134         im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
 135 #else
 136         im->ddr.csbnds[2].csbnds = 0x0000000f;
 137         im->ddr.cs_config[2] = CFG_DDR_CONFIG;
 138
 139         /* currently we use only one CS, so disable the other banks */
 140         im->ddr.cs_config[0] = 0;
 141         im->ddr.cs_config[1] = 0;
 142         im->ddr.cs_config[3] = 0;
 143
 144         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 145         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 146
 147         im->ddr.sdram_cfg =
 148                 SDRAM_CFG_SREN
 149 #if defined(CONFIG_DDR_2T_TIMING)
 150                 | SDRAM_CFG_2T_EN
 151 #endif
 152                 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
 153 #if defined (CONFIG_DDR_32BIT)
 154         /* for 32-bit mode burst length is 8 */
 155         im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
 156 #endif
 157         im->ddr.sdram_mode = CFG_DDR_MODE;
 158
 159         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 160 #endif
 161         udelay(200);
 162
 163         /* enable DDR controller */
 164         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 165         return msize;
 166 }
 167 #endif/*!CFG_SPD_EEPROM*/
 168
 169
 170 int checkboard (void)
 171 {
 172         puts("Board: Freescale MPC8349EMDS\n");
 173         return 0;
 174 }
 175
 176 /*
 177  * if MPC8349EMDS is soldered with SDRAM
 178  */
 179 #if defined(CFG_BR2_PRELIM)  \
 180         && defined(CFG_OR2_PRELIM) \
 181         && defined(CFG_LBLAWBAR2_PRELIM) \
 182         && defined(CFG_LBLAWAR2_PRELIM)
 183 /*
 184  * Initialize SDRAM memory on the Local Bus.
 185  */
 186
 187 void sdram_init(void)
 188 {
 189         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 190         volatile lbus83xx_t *lbc= &immap->lbus;
 191         uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 192
 193         puts("\n   SDRAM on Local Bus: ");
 194         print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 195
 196         /*
 197          * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 198          */
 199
 200         /* setup mtrpt, lsrt and lbcr for LB bus */
 201         lbc->lbcr = CFG_LBC_LBCR;
 202         lbc->mrtpr = CFG_LBC_MRTPR;
 203         lbc->lsrt = CFG_LBC_LSRT;
 204         asm("sync");
 205
 206         /*
 207          * Configure the SDRAM controller Machine Mode Register.
 208          */
 209         lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
 210
 211         lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
 212         asm("sync");
 213         *sdram_addr = 0xff;
 214         udelay(100);
 215
 216         lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
 217         asm("sync");
 218         /*1 times*/
 219         *sdram_addr = 0xff;
 220         udelay(100);
 221         /*2 times*/
 222         *sdram_addr = 0xff;
 223         udelay(100);
 224         /*3 times*/
 225         *sdram_addr = 0xff;
 226         udelay(100);
 227         /*4 times*/
 228         *sdram_addr = 0xff;
 229         udelay(100);
 230         /*5 times*/
 231         *sdram_addr = 0xff;
 232         udelay(100);
 233         /*6 times*/
 234         *sdram_addr = 0xff;
 235         udelay(100);
 236         /*7 times*/
 237         *sdram_addr = 0xff;
 238         udelay(100);
 239         /*8 times*/
 240         *sdram_addr = 0xff;
 241         udelay(100);
 242
 243         /* 0x58636733; mode register write operation */
 244         lbc->lsdmr = CFG_LBC_LSDMR_4;
 245         asm("sync");
 246         *sdram_addr = 0xff;
 247         udelay(100);
 248
 249         lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
 250         asm("sync");
 251         *sdram_addr = 0xff;
 252         udelay(100);
 253 }
 254 #else
 255 void sdram_init(void)
 256 {
 257         puts("   SDRAM on Local Bus is NOT available!\n");
 258 }
 259 #endif
 260
 261 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
 262 /*
 263  * ECC user commands
 264  */
 265 void ecc_print_status(void)
 266 {
 267         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 268         volatile ddr83xx_t *ddr = &immap->ddr;
 269
 270         printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
 271
 272         /* Interrupts */
 273         printf("Memory Error Interrupt Enable:\n");
 274         printf("  Multiple-Bit Error Interrupt Enable: %d\n",
 275                         (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
 276         printf("  Single-Bit Error Interrupt Enable: %d\n",
 277                         (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
 278         printf("  Memory Select Error Interrupt Enable: %d\n\n",
 279                         (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
 280
 281         /* Error disable */
 282         printf("Memory Error Disable:\n");
 283         printf("  Multiple-Bit Error Disable: %d\n",
 284                         (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
 285         printf("  Sinle-Bit Error Disable: %d\n",
 286                         (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
 287         printf("  Memory Select Error Disable: %d\n\n",
 288                         (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
 289
 290         /* Error injection */
 291         printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
 292                         ddr->data_err_inject_hi, ddr->data_err_inject_lo);
 293
 294         printf("Memory Data Path Error Injection Mask ECC:\n");
 295         printf("  ECC Mirror Byte: %d\n",
 296                         (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
 297         printf("  ECC Injection Enable: %d\n",
 298                         (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
 299         printf("  ECC Error Injection Mask: 0x%02x\n\n",
 300                         ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
 301
 302         /* SBE counter/threshold */
 303         printf("Memory Single-Bit Error Management (0..255):\n");
 304         printf("  Single-Bit Error Threshold: %d\n",
 305                         (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
 306         printf("  Single-Bit Error Counter: %d\n\n",
 307                         (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
 308
 309         /* Error detect */
 310         printf("Memory Error Detect:\n");
 311         printf("  Multiple Memory Errors: %d\n",
 312                         (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
 313         printf("  Multiple-Bit Error: %d\n",
 314                         (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
 315         printf("  Single-Bit Error: %d\n",
 316                         (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
 317         printf("  Memory Select Error: %d\n\n",
 318                         (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
 319
 320         /* Capture data */
 321         printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
 322         printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
 323                         ddr->capture_data_hi, ddr->capture_data_lo);
 324         printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
 325                 ddr->capture_ecc & CAPTURE_ECC_ECE);
 326
 327         printf("Memory Error Attributes Capture:\n");
 328         printf("  Data Beat Number: %d\n",
 329                         (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
 330         printf("  Transaction Size: %d\n",
 331                         (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
 332         printf("  Transaction Source: %d\n",
 333                         (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
 334         printf("  Transaction Type: %d\n",
 335                         (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
 336         printf("  Error Information Valid: %d\n\n",
 337                         ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
 338 }
 339
 340 int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 341 {
 342         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 343         volatile ddr83xx_t *ddr = &immap->ddr;
 344         volatile u32 val;
 345         u64 *addr, count, val64;
 346         register u64 *i;
 347
 348         if (argc > 4) {
 349                 printf ("Usage:\n%s\n", cmdtp->usage);
 350                 return 1;
 351         }
 352
 353         if (argc == 2) {
 354                 if (strcmp(argv[1], "status") == 0) {
 355                         ecc_print_status();
 356                         return 0;
 357                 } else if (strcmp(argv[1], "captureclear") == 0) {
 358                         ddr->capture_address = 0;
 359                         ddr->capture_data_hi = 0;
 360                         ddr->capture_data_lo = 0;
 361                         ddr->capture_ecc = 0;
 362                         ddr->capture_attributes = 0;
 363                         return 0;
 364                 }
 365         }
 366
 367         if (argc == 3) {
 368                 if (strcmp(argv[1], "sbecnt") == 0) {
 369                         val = simple_strtoul(argv[2], NULL, 10);
 370                         if (val > 255) {
 371                                 printf("Incorrect Counter value, should be 0..255\n");
 372                                 return 1;
 373                         }
 374
 375                         val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
 376                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
 377
 378                         ddr->err_sbe = val;
 379                         return 0;
 380                 } else if (strcmp(argv[1], "sbethr") == 0) {
 381                         val = simple_strtoul(argv[2], NULL, 10);
 382                         if (val > 255) {
 383                                 printf("Incorrect Counter value, should be 0..255\n");
 384                                 return 1;
 385                         }
 386
 387                         val = (val << ECC_ERROR_MAN_SBET_SHIFT);
 388                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
 389
 390                         ddr->err_sbe = val;
 391                         return 0;
 392                 } else if (strcmp(argv[1], "errdisable") == 0) {
 393                         val = ddr->err_disable;
 394
 395                         if (strcmp(argv[2], "+sbe") == 0) {
 396                                 val |= ECC_ERROR_DISABLE_SBED;
 397                         } else if (strcmp(argv[2], "+mbe") == 0) {
 398                                 val |= ECC_ERROR_DISABLE_MBED;
 399                         } else if (strcmp(argv[2], "+mse") == 0) {
 400                                 val |= ECC_ERROR_DISABLE_MSED;
 401                         } else if (strcmp(argv[2], "+all") == 0) {
 402                                 val |= (ECC_ERROR_DISABLE_SBED |
 403                                         ECC_ERROR_DISABLE_MBED |
 404                                         ECC_ERROR_DISABLE_MSED);
 405                         } else if (strcmp(argv[2], "-sbe") == 0) {
 406                                 val &= ~ECC_ERROR_DISABLE_SBED;
 407                         } else if (strcmp(argv[2], "-mbe") == 0) {
 408                                 val &= ~ECC_ERROR_DISABLE_MBED;
 409                         } else if (strcmp(argv[2], "-mse") == 0) {
 410                                 val &= ~ECC_ERROR_DISABLE_MSED;
 411                         } else if (strcmp(argv[2], "-all") == 0) {
 412                                 val &= ~(ECC_ERROR_DISABLE_SBED |
 413                                         ECC_ERROR_DISABLE_MBED |
 414                                         ECC_ERROR_DISABLE_MSED);
 415                         } else {
 416                                 printf("Incorrect err_disable field\n");
 417                                 return 1;
 418                         }
 419
 420                         ddr->err_disable = val;
 421                         __asm__ __volatile__ ("sync");
 422                         __asm__ __volatile__ ("isync");
 423                         return 0;
 424                 } else if (strcmp(argv[1], "errdetectclr") == 0) {
 425                         val = ddr->err_detect;
 426
 427                         if (strcmp(argv[2], "mme") == 0) {
 428                                 val |= ECC_ERROR_DETECT_MME;
 429                         } else if (strcmp(argv[2], "sbe") == 0) {
 430                                 val |= ECC_ERROR_DETECT_SBE;
 431                         } else if (strcmp(argv[2], "mbe") == 0) {
 432                                 val |= ECC_ERROR_DETECT_MBE;
 433                         } else if (strcmp(argv[2], "mse") == 0) {
 434                                 val |= ECC_ERROR_DETECT_MSE;
 435                         } else if (strcmp(argv[2], "all") == 0) {
 436                                 val |= (ECC_ERROR_DETECT_MME |
 437                                         ECC_ERROR_DETECT_MBE |
 438                                         ECC_ERROR_DETECT_SBE |
 439                                         ECC_ERROR_DETECT_MSE);
 440                         } else {
 441                                 printf("Incorrect err_detect field\n");
 442                                 return 1;
 443                         }
 444
 445                         ddr->err_detect = val;
 446                         return 0;
 447                 } else if (strcmp(argv[1], "injectdatahi") == 0) {
 448                         val = simple_strtoul(argv[2], NULL, 16);
 449
 450                         ddr->data_err_inject_hi = val;
 451                         return 0;
 452                 } else if (strcmp(argv[1], "injectdatalo") == 0) {
 453                         val = simple_strtoul(argv[2], NULL, 16);
 454
 455                         ddr->data_err_inject_lo = val;
 456                         return 0;
 457                 } else if (strcmp(argv[1], "injectecc") == 0) {
 458                         val = simple_strtoul(argv[2], NULL, 16);
 459                         if (val > 0xff) {
 460                                 printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
 461                                 return 1;
 462                         }
 463                         val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
 464
 465                         ddr->ecc_err_inject = val;
 466                         return 0;
 467                 } else if (strcmp(argv[1], "inject") == 0) {
 468                         val = ddr->ecc_err_inject;
 469
 470                         if (strcmp(argv[2], "en") == 0)
 471                                 val |= ECC_ERR_INJECT_EIEN;
 472                         else if (strcmp(argv[2], "dis") == 0)
 473                                 val &= ~ECC_ERR_INJECT_EIEN;
 474                         else
 475                                 printf("Incorrect command\n");
 476
 477                         ddr->ecc_err_inject = val;
 478                         __asm__ __volatile__ ("sync");
 479                         __asm__ __volatile__ ("isync");
 480                         return 0;
 481                 } else if (strcmp(argv[1], "mirror") == 0) {
 482                         val = ddr->ecc_err_inject;
 483
 484                         if (strcmp(argv[2], "en") == 0)
 485                                 val |= ECC_ERR_INJECT_EMB;
 486                         else if (strcmp(argv[2], "dis") == 0)
 487                                 val &= ~ECC_ERR_INJECT_EMB;
 488                         else
 489                                 printf("Incorrect command\n");
 490
 491                         ddr->ecc_err_inject = val;
 492                         return 0;
 493                 }
 494         }
 495
 496         if (argc == 4) {
 497                 if (strcmp(argv[1], "test") == 0) {
 498                         addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
 499                         count = simple_strtoul(argv[3], NULL, 16);
 500
 501                         if ((u32)addr % 8) {
 502                                 printf("Address not alligned on double word boundary\n");
 503                                 return 1;
 504                         }
 505
 506                         disable_interrupts();
 507                         icache_disable();
 508
 509                         for (i = addr; i < addr + count; i++) {
 510                                 /* enable injects */
 511                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 512                                 __asm__ __volatile__ ("sync");
 513                                 __asm__ __volatile__ ("isync");
 514
 515                                 /* write memory location injecting errors */
 516                                 *i = 0x1122334455667788ULL;
 517                                 __asm__ __volatile__ ("sync");
 518
 519                                 /* disable injects */
 520                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 521                                 __asm__ __volatile__ ("sync");
 522                                 __asm__ __volatile__ ("isync");
 523
 524                                 /* read data, this generates ECC error */
 525                                 val64 = *i;
 526                                 __asm__ __volatile__ ("sync");
 527
 528                                 /* disable errors for ECC */
 529                                 ddr->err_disable |= ~ECC_ERROR_ENABLE;
 530                                 __asm__ __volatile__ ("sync");
 531                                 __asm__ __volatile__ ("isync");
 532
 533                                 /* re-initialize memory, write the location again
 534                                  * NOT injecting errors this time */
 535                                 *i = 0xcafecafecafecafeULL;
 536                                 __asm__ __volatile__ ("sync");
 537
 538                                 /* enable errors for ECC */
 539                                 ddr->err_disable &= ECC_ERROR_ENABLE;
 540                                 __asm__ __volatile__ ("sync");
 541                                 __asm__ __volatile__ ("isync");
 542                         }
 543
 544                         icache_enable();
 545                         enable_interrupts();
 546
 547                         return 0;
 548                 }
 549         }
 550
 551         printf ("Usage:\n%s\n", cmdtp->usage);
 552         return 1;
 553 }
 554
 555 U_BOOT_CMD(
 556         ecc,     4,     0,      do_ecc,
 557         "ecc     - support for DDR ECC features\n",
 558         "status              - print out status info\n"
 559         "ecc captureclear        - clear capture regs data\n"
 560         "ecc sbecnt <val>        - set Single-Bit Error counter\n"
 561         "ecc sbethr <val>        - set Single-Bit Threshold\n"
 562         "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
 563         "  [-|+]sbe - Single-Bit Error\n"
 564         "  [-|+]mbe - Multiple-Bit Error\n"
 565         "  [-|+]mse - Memory Select Error\n"
 566         "  [-|+]all - all errors\n"
 567         "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
 568         "  mme - Multiple Memory Errors\n"
 569         "  sbe - Single-Bit Error\n"
 570         "  mbe - Multiple-Bit Error\n"
 571         "  mse - Memory Select Error\n"
 572         "  all - all errors\n"
 573         "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
 574         "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
 575         "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
 576         "ecc inject <en|dis>    - enable/disable error injection\n"
 577         "ecc mirror <en|dis>    - enable/disable mirror byte\n"
 578         "ecc test <addr> <cnt>  - test mem region:\n"
 579         "  - enables injects\n"
 580         "  - writes pattern injecting errors\n"
 581         "  - disables injects\n"
 582         "  - reads pattern back, generates error\n"
 583         "  - re-inits memory"
 584 );
 585 #endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
 586
 587 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 588 void
 589 ft_board_setup(void *blob, bd_t *bd)
 590 {
 591         u32 *p;
 592         int len;
 593
 594 #ifdef CONFIG_PCI
 595         ft_pci_setup(blob, bd);
 596 #endif
 597         ft_cpu_setup(blob, bd);
 598
 599         p = ft_get_prop(blob, "/memory/reg", &len);
 600         if (p != NULL) {
 601                 *p++ = cpu_to_be32(bd->bi_memstart);
 602                 *p = cpu_to_be32(bd->bi_memsize);
 603         }
 604 }
 605 #endif