2 * See file CREDITS for list of people who contributed to this
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/global_data.h>
26 #include <asm/mpc8349_pci.h>
31 /* System RAM mapped to PCI space */
32 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
33 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
35 #ifndef CONFIG_PCI_PNP
36 static struct pci_config_table pci_mpc83xxads_config_table[] = {
37 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
38 PCI_IDSEL_NUMBER, PCI_ANY_ID,
39 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
41 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
48 static struct pci_controller pci_hose[] = {
50 #ifndef CONFIG_PCI_PNP
51 config_table:pci_mpc83xxads_config_table,
55 #ifndef CONFIG_PCI_PNP
56 config_table:pci_mpc83xxads_config_table,
61 /**************************************************************************
63 * pib_init() -- initialize the PCA9555PW IO expander on the PIB board
71 * Assign PIB PMC slot to desired PCI bus
73 mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
74 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
77 i2c_write(0x23, 0x6, 1, &val8, 1);
78 i2c_write(0x23, 0x7, 1, &val8, 1);
80 i2c_write(0x23, 0x2, 1, &val8, 1);
81 i2c_write(0x23, 0x3, 1, &val8, 1);
84 i2c_write(0x26, 0x6, 1, &val8, 1);
86 i2c_write(0x26, 0x7, 1, &val8, 1);
87 #if defined(PCI_64BIT)
88 val8 = 0xf4; /* PMC2:PCI1/64-bit */
89 #elif defined(PCI_ALL_PCI1)
90 val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
91 #elif defined(PCI_ONE_PCI1)
92 val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
94 val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
96 i2c_write(0x26, 0x2, 1, &val8, 1);
98 i2c_write(0x26, 0x3, 1, &val8, 1);
100 i2c_write(0x27, 0x6, 1, &val8, 1);
101 i2c_write(0x27, 0x7, 1, &val8, 1);
103 i2c_write(0x27, 0x2, 1, &val8, 1);
105 i2c_write(0x27, 0x3, 1, &val8, 1);
108 #if defined(PCI_64BIT)
109 printf("PCI1: 64-bit on PMC2\n");
110 #elif defined(PCI_ALL_PCI1)
111 printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
112 #elif defined(PCI_ONE_PCI1)
113 printf("PCI1: 32-bit on PMC1\n");
114 printf("PCI2: 32-bit on PMC2, PMC3\n");
116 printf("PCI1: 32-bit on PMC1, PMC2\n");
117 printf("PCI2: 32-bit on PMC3\n");
121 /**************************************************************************
124 * NOTICE: PCI2 is not currently supported
130 DECLARE_GLOBAL_DATA_PTR;
131 volatile immap_t * immr;
132 volatile clk8349_t * clk;
133 volatile law8349_t * pci_law;
134 volatile pot8349_t * pci_pot;
135 volatile pcictrl8349_t * pci_ctrl;
136 volatile pciconf8349_t * pci_conf;
139 struct pci_controller * hose;
141 immr = (immap_t *)CFG_IMMRBAR;
142 clk = (clk8349_t *)&immr->clk;
143 pci_law = immr->sysconf.pcilaw;
144 pci_pot = immr->ios.pot;
145 pci_ctrl = immr->pci_ctrl;
146 pci_conf = immr->pci_conf;
153 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
158 clk->occr = 0xff000000;
162 * Release PCI RST Output signal
168 #ifdef CONFIG_MPC83XX_PCI2
174 /* We need to wait at least a 1sec based on PCI specs */
178 for (i = 0; i < 1000; ++i)
183 * Configure PCI Local Access Windows
185 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
186 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
188 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
189 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
192 * Configure PCI Outbound Translation Windows
195 /* PCI1 mem space - prefetch */
196 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
197 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
198 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
201 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
202 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
203 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
205 /* PCI1 mmio - non-prefetch mem space */
206 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
207 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
208 pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
211 * Configure PCI Inbound Translation Windows
214 /* we need RAM mapped to PCI space for the devices to
215 * access main memory */
216 pci_ctrl[0].pitar1 = 0x0;
217 pci_ctrl[0].pibar1 = 0x0;
218 pci_ctrl[0].piebar1 = 0x0;
219 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
221 hose->first_busno = 0;
222 hose->last_busno = 0xff;
224 /* PCI memory prefetch space */
225 pci_set_region(hose->regions + 0,
229 PCI_REGION_MEM|PCI_REGION_PREFETCH);
231 /* PCI memory space */
232 pci_set_region(hose->regions + 1,
239 pci_set_region(hose->regions + 2,
245 /* System memory space */
246 pci_set_region(hose->regions + 3,
247 CONFIG_PCI_SYS_MEM_BUS,
248 CONFIG_PCI_SYS_MEM_PHYS,
250 PCI_REGION_MEM | PCI_REGION_MEMORY);
252 hose->region_count = 4;
254 pci_setup_indirect(hose,
255 (CFG_IMMRBAR+0x8300),
256 (CFG_IMMRBAR+0x8304));
258 pci_register_hose(hose);
261 * Write to Command register
264 pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
266 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
267 pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
271 * Clear non-reserved bits in status register.
273 pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
275 pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
277 pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_CACHE_LINE_SIZE,
280 #ifdef CONFIG_PCI_SCAN_SHOW
281 printf("PCI: Bus Dev VenId DevId Class Int\n");
286 hose->last_busno = pci_hose_scan(hose);
288 #ifdef CONFIG_MPC83XX_PCI2
292 * Configure PCI Outbound Translation Windows
295 /* PCI2 mem space - prefetch */
296 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
297 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
298 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
301 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
302 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
303 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
305 /* PCI2 mmio - non-prefetch mem space */
306 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
307 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
308 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
311 * Configure PCI Inbound Translation Windows
314 /* we need RAM mapped to PCI space for the devices to
315 * access main memory */
316 pci_ctrl[1].pitar1 = 0x0;
317 pci_ctrl[1].pibar1 = 0x0;
318 pci_ctrl[1].piebar1 = 0x0;
319 pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
321 hose->first_busno = pci_hose[0].last_busno + 1;
322 hose->last_busno = 0xff;
324 /* PCI memory prefetch space */
325 pci_set_region(hose->regions + 0,
329 PCI_REGION_MEM|PCI_REGION_PREFETCH);
331 /* PCI memory space */
332 pci_set_region(hose->regions + 1,
339 pci_set_region(hose->regions + 2,
345 /* System memory space */
346 pci_set_region(hose->regions + 3,
347 CONFIG_PCI_SYS_MEM_BUS,
348 CONFIG_PCI_SYS_MEM_PHYS,
350 PCI_REGION_MEM | PCI_REGION_MEMORY);
352 hose->region_count = 4;
354 pci_setup_indirect(hose,
355 (CFG_IMMRBAR+0x8380),
356 (CFG_IMMRBAR+0x8384));
358 pci_register_hose(hose);
361 * Write to Command register
364 pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
366 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
367 pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
371 * Clear non-reserved bits in status register.
373 pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
375 pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
377 pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_CACHE_LINE_SIZE,
383 hose->last_busno = pci_hose_scan(hose);
387 #endif /* CONFIG_PCI */