board/mini-box/picosam9g45/picosam9g45.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board
   4  * (C) Copyright 2015 Inter Act B.V.
   5  *
   6  * Based on:
   7  * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
   8  * (C) Copyright 2007-2008
   9  * Stelian Pop <stelian@popies.net>
  10  * Lead Tech Design <www.leadtechdesign.com>
  11  */
  12
  13 #include <common.h>
  14 #include <init.h>
  15 #include <vsprintf.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/clk.h>
  18 #include <asm/arch/at91sam9g45_matrix.h>
  19 #include <asm/arch/at91sam9_smc.h>
  20 #include <asm/arch/at91_common.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/clk.h>
  23 #include <lcd.h>
  24 #include <linux/mtd/rawnand.h>
  25 #include <atmel_lcdc.h>
  26 #include <atmel_mci.h>
  27 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  28 #include <net.h>
  29 #endif
  30 #include <netdev.h>
  31 #include <asm/mach-types.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 /* ------------------------------------------------------------------------- */
  36 /*
  37  * Miscelaneous platform dependent initialisations
  38  */
  39
  40 #if defined(CONFIG_SPL_BUILD)
  41 #include <spl.h>
  42
  43 void at91_spl_board_init(void)
  44 {
  45 #ifdef CONFIG_SYS_USE_MMC
  46         at91_mci_hw_init();
  47 #endif
  48 }
  49
  50 #include <asm/arch/atmel_mpddrc.h>
  51 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  52 {
  53         ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  54
  55         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  56                     ATMEL_MPDDRC_CR_NR_ROW_14 |
  57                     ATMEL_MPDDRC_CR_DQMS_SHARED |
  58                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
  59
  60         ddr2->rtr = 0x24b;
  61
  62         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
  63                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
  64                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
  65                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
  66                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
  67                       1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
  68                       1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
  69                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
  70
  71         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
  72                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  73                       16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  74                       14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  75
  76         ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  77                       0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  78                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  79                       2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  80 }
  81
  82 void mem_init(void)
  83 {
  84         struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  85         struct atmel_mpddrc_config ddr2;
  86         unsigned long csa;
  87
  88         ddr2_conf(&ddr2);
  89
  90         at91_system_clk_enable(AT91_PMC_DDR);
  91
  92         /* Chip select 1 is for DDR2/SDRAM */
  93         csa = readl(&mat->ebicsa);
  94         csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
  95         csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
  96         writel(csa, &mat->ebicsa);
  97
  98         /* DDRAM2 Controller initialize */
  99         ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
 100         ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2);
 101 }
 102 #endif
 103
 104 #ifdef CONFIG_CMD_USB
 105 static void picosam9g45_usb_hw_init(void)
 106 {
 107         at91_periph_clk_enable(ATMEL_ID_PIODE);
 108
 109         at91_set_gpio_output(AT91_PIN_PD1, 0);
 110         at91_set_gpio_output(AT91_PIN_PD3, 0);
 111 }
 112 #endif
 113
 114 #ifdef CONFIG_MACB
 115 static void picosam9g45_macb_hw_init(void)
 116 {
 117         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
 118
 119         at91_periph_clk_enable(ATMEL_ID_EMAC);
 120
 121         /*
 122          * Disable pull-up on:
 123          *      RXDV (PA15) => PHY normal mode (not Test mode)
 124          *      ERX0 (PA12) => PHY ADDR0
 125          *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
 126          *
 127          * PHY has internal pull-down
 128          */
 129         writel(pin_to_mask(AT91_PIN_PA15) |
 130                pin_to_mask(AT91_PIN_PA12) |
 131                pin_to_mask(AT91_PIN_PA13),
 132                &pioa->pudr);
 133
 134         at91_phy_reset();
 135
 136         /* Re-enable pull-up */
 137         writel(pin_to_mask(AT91_PIN_PA15) |
 138                pin_to_mask(AT91_PIN_PA12) |
 139                pin_to_mask(AT91_PIN_PA13),
 140                &pioa->puer);
 141
 142         /* And the pins. */
 143         at91_macb_hw_init();
 144 }
 145 #endif
 146
 147 #ifdef CONFIG_LCD
 148
 149 vidinfo_t panel_info = {
 150         .vl_col =               480,
 151         .vl_row =               272,
 152         .vl_clk =               9000000,
 153         .vl_sync =              ATMEL_LCDC_INVLINE_NORMAL |
 154                                 ATMEL_LCDC_INVFRAME_NORMAL,
 155         .vl_bpix =              3,
 156         .vl_tft =               1,
 157         .vl_hsync_len =         45,
 158         .vl_left_margin =       1,
 159         .vl_right_margin =      1,
 160         .vl_vsync_len =         1,
 161         .vl_upper_margin =      40,
 162         .vl_lower_margin =      1,
 163         .mmio =                 ATMEL_BASE_LCDC,
 164 };
 165
 166
 167 void lcd_enable(void)
 168 {
 169         at91_set_A_periph(AT91_PIN_PE6, 1);     /* power up */
 170 }
 171
 172 void lcd_disable(void)
 173 {
 174         at91_set_A_periph(AT91_PIN_PE6, 0);     /* power down */
 175 }
 176
 177 static void picosam9g45_lcd_hw_init(void)
 178 {
 179         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 180         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
 181         at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
 182         at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
 183         at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
 184
 185         at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
 186         at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
 187         at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
 188         at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
 189         at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
 190         at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
 191         at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
 192         at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
 193         at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
 194         at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
 195         at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
 196         at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
 197         at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
 198         at91_set_B_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
 199         at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
 200         at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
 201         at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
 202         at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
 203         at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
 204         at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
 205         at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
 206         at91_set_B_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
 207         at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
 208         at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
 209
 210         at91_periph_clk_enable(ATMEL_ID_LCDC);
 211
 212         gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
 213 }
 214
 215 #ifdef CONFIG_LCD_INFO
 216 #include <nand.h>
 217 #include <version.h>
 218
 219 void lcd_show_board_info(void)
 220 {
 221         ulong dram_size;
 222         int i;
 223         char temp[32];
 224
 225         lcd_printf("%s\n", U_BOOT_VERSION);
 226         lcd_printf("(C) 2015 Inter Act B.V.\n");
 227         lcd_printf("support@interact.nl\n");
 228         lcd_printf("%s CPU at %s MHz\n",
 229                    ATMEL_CPU_NAME,
 230                    strmhz(temp, get_cpu_clk_rate()));
 231
 232         dram_size = 0;
 233         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 234                 dram_size += gd->bd->bi_dram[i].size;
 235         lcd_printf("  %ld MB SDRAM\n", dram_size >> 20);
 236 }
 237 #endif /* CONFIG_LCD_INFO */
 238 #endif
 239
 240 #ifdef CONFIG_GENERIC_ATMEL_MCI
 241 int board_mmc_init(bd_t *bis)
 242 {
 243         at91_mci_hw_init();
 244
 245         return atmel_mci_init((void *)ATMEL_BASE_MCI0);
 246 }
 247 #endif
 248
 249 int board_early_init_f(void)
 250 {
 251         at91_seriald_hw_init();
 252         return 0;
 253 }
 254
 255 int board_init(void)
 256 {
 257         gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
 258
 259         /* adress of boot parameters */
 260         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 261
 262 #ifdef CONFIG_CMD_USB
 263         picosam9g45_usb_hw_init();
 264 #endif
 265 #ifdef CONFIG_ATMEL_SPI
 266         at91_spi0_hw_init(1 << 4);
 267 #endif
 268 #ifdef CONFIG_MACB
 269         picosam9g45_macb_hw_init();
 270 #endif
 271 #ifdef CONFIG_LCD
 272         picosam9g45_lcd_hw_init();
 273 #endif
 274         return 0;
 275 }
 276
 277 int dram_init(void)
 278 {
 279         gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
 280                         + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
 281
 282         return 0;
 283 }
 284
 285 int dram_init_banksize(void)
 286 {
 287         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 288         gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
 289                                                         PHYS_SDRAM_1_SIZE);
 290         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 291         gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
 292                                                         PHYS_SDRAM_2_SIZE);
 293
 294         return 0;
 295 }
 296
 297 #ifdef CONFIG_RESET_PHY_R
 298 void reset_phy(void)
 299 {
 300 }
 301 #endif
 302
 303 int board_eth_init(bd_t *bis)
 304 {
 305         int rc = 0;
 306 #ifdef CONFIG_MACB
 307         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 308 #endif
 309         return rc;
 310 }
 311
 312 /* SPI chip select control */
 313 #ifdef CONFIG_ATMEL_SPI
 314 #include <spi.h>
 315
 316 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 317 {
 318         return bus == 0 && cs < 2;
 319 }
 320
 321 void spi_cs_activate(struct spi_slave *slave)
 322 {
 323         switch (slave->cs) {
 324         case 1:
 325                 at91_set_gpio_output(AT91_PIN_PB18, 0);
 326                 break;
 327         case 0:
 328         default:
 329                 at91_set_gpio_output(AT91_PIN_PB3, 0);
 330                 break;
 331         }
 332 }
 333
 334 void spi_cs_deactivate(struct spi_slave *slave)
 335 {
 336         switch (slave->cs) {
 337         case 1:
 338                 at91_set_gpio_output(AT91_PIN_PB18, 1);
 339                 break;
 340         case 0:
 341         default:
 342                 at91_set_gpio_output(AT91_PIN_PB3, 1);
 343         break;
 344         }
 345 }
 346 #endif /* CONFIG_ATMEL_SPI */