2 * Copyright (C) 2006 Atmel Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/sdram.h>
27 #include <asm/arch/clk.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/hmatrix.h>
32 #define SM_PM_GCCTRL 0x0060
34 DECLARE_GLOBAL_DATA_PTR;
36 static const struct sdram_config sdram_config = {
37 .data_bits = SDRAM_DATA_16BIT,
49 .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
52 int board_early_init_f(void)
54 /* Enable SDRAM in the EBI mux */
55 hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
60 /* enable higher address lines for larger flash devices */
61 gpio_select_periph_A(GPIO_PIN_PE16, 0); /* ADDR23 */
62 gpio_select_periph_A(GPIO_PIN_PE17, 0); /* ADDR24 */
63 gpio_select_periph_A(GPIO_PIN_PE18, 0); /* ADDR25 */
65 /* enable data flash chip select */
66 gpio_select_periph_A(GPIO_PIN_PE25, 0); /* NCS2 */
68 /* de-assert "force sys reset" pin */
69 gpio_set_value(GPIO_PIN_PD15, 1); /* FORCE RESET */
70 gpio_select_pio(GPIO_PIN_PD15, GPIOF_OUTPUT);
74 gpio_select_pio(GPIO_PIN_PE19, 0);
75 gpio_select_pio(GPIO_PIN_PE20, 0);
76 gpio_select_pio(GPIO_PIN_PE23, 0);
77 /* main board type inputs */
78 gpio_select_pio(GPIO_PIN_PB19, 0);
79 gpio_select_pio(GPIO_PIN_PB29, 0);
80 /* DEBUG input (use weak pullup) */
81 gpio_select_pio(GPIO_PIN_PE21, GPIOF_PULLUP);
83 /* are we suppressing the console ? */
84 if (gpio_get_value(GPIO_PIN_PE21) == 1)
85 gd->flags |= GD_FLG_SILENT;
88 gpio_select_pio(GPIO_PIN_PE24, 0);
89 gpio_set_value(GPIO_PIN_PC18, 1); /* PHY RESET */
90 gpio_select_pio(GPIO_PIN_PC18, GPIOF_OUTPUT);
92 /* GCLK0 - 10MHz clock */
93 writel(0x00000004, (void *)SM_BASE + SM_PM_GCCTRL);
94 gpio_select_periph_A(GPIO_PIN_PA30, 0);
98 /* release phys reset */
99 gpio_set_value(GPIO_PIN_PC18, 0); /* PHY RESET (Release) */
101 #if defined(CONFIG_MACB)
102 /* init macb0 pins */
103 gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */
104 gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */
105 gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */
106 gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */
107 gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */
108 gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */
109 gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */
110 gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */
111 gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */
112 gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */
113 #if !defined(CONFIG_RMII)
114 gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */
115 gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */
116 gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */
117 gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */
118 gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */
119 gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */
120 gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */
121 gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */
124 /* init macb1 pins */
125 gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */
126 gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */
127 gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */
128 gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */
129 gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */
130 gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */
131 gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */
132 gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */
133 gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */
134 gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */
135 #if !defined(CONFIG_RMII)
136 gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */
137 gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */
138 gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */
139 gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */
140 gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */
141 gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */
142 gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */
143 gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */
147 #if defined(CONFIG_MMC)
154 phys_size_t initdram(int board_type)
156 unsigned long expected_size;
157 unsigned long actual_size;
160 sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
162 expected_size = sdram_init(sdram_base, &sdram_config);
163 actual_size = get_ram_size(sdram_base, expected_size);
165 unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
167 if (expected_size != actual_size)
168 printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
169 actual_size >> 20, expected_size >> 20);
174 void board_init_info(void)
176 gd->bd->bi_phy_id[0] = 0x01;
177 gd->bd->bi_phy_id[1] = 0x03;
180 /* SPI chip select control */
181 #ifdef CONFIG_ATMEL_SPI
184 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
186 return (bus == 0) && (cs == 0);
189 void spi_cs_activate(struct spi_slave *slave)
193 void spi_cs_deactivate(struct spi_slave *slave)
196 #endif /* CONFIG_ATMEL_SPI */
198 #ifdef CONFIG_CMD_NET
199 int board_eth_init(bd_t *bi)
201 macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
202 macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);