2 * (C) Copyright 2011 Alex Dubov <oakad@yahoo.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
26 #include <asm/immap_85xx.h>
27 #include <asm/fsl_law.h>
31 #include <fdt_support.h>
34 * Initialize Local Bus
36 void local_bus_init(void)
38 fsl_lbc_t *lbc = LBC_BASE_ADDR;
40 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
41 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
46 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
47 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
49 puts("Board: Mercury Computer Systems, Inc. MPQ-101 ");
50 #ifdef CONFIG_PHYS_64BIT
51 puts("(36-bit addrmap) ");
56 * Initialize local bus.
61 * Hack TSEC 3 and 4 IO voltages.
63 out_be32(&gur->tsec34ioovcr, 0xe7e0); /* 1110 0111 1110 0xxx */
65 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
66 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
70 phys_size_t fixed_sdram(void)
72 ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
73 const char *p_mode = getenv("perf_mode");
75 puts("Initializing....");
77 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
78 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
80 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
81 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
83 if (p_mode && !strcmp("performance", p_mode)) {
84 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_PERF);
85 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_PERF);
86 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_PERF);
87 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_PERF);
88 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_PERF);
90 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
91 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
92 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
93 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
94 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
97 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
98 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
103 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
107 return ((phys_size_t)1) << CONFIG_SYS_SDRAM_SIZE_LOG;
110 void pci_init_board(void)
112 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
114 /* PCI is disabled */
115 out_be32(&gur->devdisr, in_be32(&gur->devdisr)
116 | MPC85xx_DEVDISR_PCI1
117 | MPC85xx_DEVDISR_PCI2
118 | MPC85xx_DEVDISR_PCIE);
122 #if defined(CONFIG_OF_BOARD_SETUP)
124 void ft_board_setup(void *blob, bd_t *bd)
126 ft_cpu_setup(blob, bd);