board/menlo/m53menlo/m53menlo.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Menlosystems M53Menlo board
   4  *
   5  * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
   6  * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/iomux-mx53.h>
  17 #include <asm/mach-imx/mx5_video.h>
  18 #include <asm/mach-imx/video.h>
  19 #include <asm/gpio.h>
  20 #include <asm/spl.h>
  21 #include <fdt_support.h>
  22 #include <fsl_esdhc.h>
  23 #include <i2c.h>
  24 #include <ipu_pixfmt.h>
  25 #include <linux/errno.h>
  26 #include <linux/fb.h>
  27 #include <mmc.h>
  28 #include <netdev.h>
  29 #include <spl.h>
  30 #include <splash.h>
  31 #include <usb/ehci-ci.h>
  32 #include <video_console.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 static u32 mx53_dram_size[2];
  37
  38 ulong board_get_usable_ram_top(ulong total_size)
  39 {
  40         /*
  41          * WARNING: We must override get_effective_memsize() function here
  42          * to report only the size of the first DRAM bank. This is to make
  43          * U-Boot relocator place U-Boot into valid memory, that is, at the
  44          * end of the first DRAM bank. If we did not override this function
  45          * like so, U-Boot would be placed at the address of the first DRAM
  46          * bank + total DRAM size - sizeof(uboot), which in the setup where
  47          * each DRAM bank contains 512MiB of DRAM would result in placing
  48          * U-Boot into invalid memory area close to the end of the first
  49          * DRAM bank.
  50          */
  51         return PHYS_SDRAM_2 + mx53_dram_size[1];
  52 }
  53
  54 int dram_init(void)
  55 {
  56         mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
  57         mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
  58
  59         gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
  60
  61         return 0;
  62 }
  63
  64 int dram_init_banksize(void)
  65 {
  66         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  67         gd->bd->bi_dram[0].size = mx53_dram_size[0];
  68
  69         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  70         gd->bd->bi_dram[1].size = mx53_dram_size[1];
  71
  72         return 0;
  73 }
  74
  75 static void setup_iomux_uart(void)
  76 {
  77         static const iomux_v3_cfg_t uart_pads[] = {
  78                 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  79                 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  80         };
  81
  82         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  83 }
  84
  85 static void setup_iomux_fec(void)
  86 {
  87         static const iomux_v3_cfg_t fec_pads[] = {
  88                 /* MDIO pads */
  89                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  90                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  91                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  92
  93                 /* FEC 0 pads */
  94                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  95                              PAD_CTL_HYS | PAD_CTL_PKE),
  96                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  97                              PAD_CTL_HYS | PAD_CTL_PKE),
  98                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  99                              PAD_CTL_HYS | PAD_CTL_PKE),
 100                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
 101                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 102                              PAD_CTL_HYS | PAD_CTL_PKE),
 103                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 104                              PAD_CTL_HYS | PAD_CTL_PKE),
 105                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 106                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 107
 108                 /* FEC 1 pads */
 109                 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
 110                              PAD_CTL_HYS | PAD_CTL_PKE),
 111                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
 112                              PAD_CTL_HYS | PAD_CTL_PKE),
 113                 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
 114                              PAD_CTL_HYS | PAD_CTL_PKE),
 115                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
 116                              PAD_CTL_HYS | PAD_CTL_PKE),
 117                 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
 118                              PAD_CTL_HYS | PAD_CTL_PKE),
 119                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
 120                 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
 121                              PAD_CTL_HYS | PAD_CTL_PKE),
 122                 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
 123         };
 124
 125         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 126 }
 127
 128 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
 129 {
 130         static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 131         int ret;
 132
 133         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 134         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 135
 136         /*
 137          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 138          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 139          */
 140         ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
 141         if (ret)
 142                 puts("IPU:   Failed to configure LDB clock\n");
 143
 144         /* Configure CCM_CSCMR2 */
 145         clrsetbits_le32(&mxc_ccm->cscmr2,
 146                         (0x7 << 26) | BIT(10) | BIT(8),
 147                         (0x5 << 26) | BIT(10) | BIT(8));
 148
 149         /* Configure LDB_CTRL */
 150         writel(0x201, 0x53fa8008);
 151 }
 152
 153 static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
 154 {
 155         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 156
 157         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 158         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 159
 160         /*
 161          * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
 162          * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 163          */
 164         enable_lvds_clock(dev, 63);
 165 }
 166
 167 static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
 168 {
 169         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 170
 171         /*
 172          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 173          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 174          */
 175         enable_lvds_clock(dev, 233);
 176
 177         /* For ETM0700G0DH6 model, this may be enabled after the clock. */
 178         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 179 }
 180
 181 static const char *lvds_compat_string;
 182
 183 static int detect_lvds(struct display_info_t const *dev)
 184 {
 185         u8 touchid[23];
 186         u8 *touchptr = &touchid[0];
 187         int ret;
 188
 189         ret = i2c_set_bus_num(0);
 190         if (ret)
 191                 return 0;
 192
 193         /* Touchscreen is at address 0x38, ID register is 0xbb. */
 194         ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
 195         if (ret)
 196                 return 0;
 197
 198         /* EP0430 prefixes the response with 0xbb, skip it. */
 199         if (*touchptr == 0xbb)
 200                 touchptr++;
 201
 202         /* Skip the 'EP' prefix. */
 203         touchptr += 2;
 204
 205         ret = !memcmp(touchptr, &dev->mode.name[7], 4);
 206         if (ret)
 207                 lvds_compat_string = dev->mode.name;
 208
 209         return ret;
 210 }
 211
 212 void board_preboot_os(void)
 213 {
 214         /* Power off the LCD to prevent awful color flicker */
 215         gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
 216 }
 217
 218 int ft_board_setup(void *blob, bd_t *bd)
 219 {
 220         if (lvds_compat_string)
 221                 do_fixup_by_path_string(blob, "/panel", "compatible",
 222                                         lvds_compat_string);
 223
 224         return 0;
 225 }
 226
 227 struct display_info_t const displays[] = {
 228         {
 229                 .bus    = 0,
 230                 .addr   = 0,
 231                 .detect = detect_lvds,
 232                 .enable = enable_lvds_etm0430g0dh6,
 233                 .pixfmt = IPU_PIX_FMT_RGB666,
 234                 .mode   = {
 235                         .name           = "edt,etm0430g0dh6",
 236                         .refresh        = 60,
 237                         .xres           = 480,
 238                         .yres           = 272,
 239                         .pixclock       = 111111, /* picosecond (9 MHz) */
 240                         .left_margin    = 2,
 241                         .right_margin   = 2,
 242                         .upper_margin   = 2,
 243                         .lower_margin   = 2,
 244                         .hsync_len      = 41,
 245                         .vsync_len      = 10,
 246                         .sync           = 0x40000000,
 247                         .vmode          = FB_VMODE_NONINTERLACED
 248                 }
 249         }, {
 250                 .bus    = 0,
 251                 .addr   = 0,
 252                 .detect = detect_lvds,
 253                 .enable = enable_lvds_etm0700g0dh6,
 254                 .pixfmt = IPU_PIX_FMT_RGB666,
 255                 .mode   = {
 256                         .name           = "edt,etm0700g0dh6",
 257                         .refresh        = 60,
 258                         .xres           = 800,
 259                         .yres           = 480,
 260                         .pixclock       = 30048, /* picosecond (33.28 MHz) */
 261                         .left_margin    = 40,
 262                         .right_margin   = 88,
 263                         .upper_margin   = 10,
 264                         .lower_margin   = 33,
 265                         .hsync_len      = 128,
 266                         .vsync_len      = 2,
 267                         .sync           = FB_SYNC_EXT,
 268                         .vmode          = FB_VMODE_NONINTERLACED
 269                 }
 270         }
 271 };
 272
 273 size_t display_count = ARRAY_SIZE(displays);
 274
 275 #ifdef CONFIG_SPLASH_SCREEN
 276 static struct splash_location default_splash_locations[] = {
 277         {
 278                 .name           = "mmc_fs",
 279                 .storage        = SPLASH_STORAGE_MMC,
 280                 .flags          = SPLASH_STORAGE_FS,
 281                 .devpart        = "0:1",
 282         },
 283 };
 284
 285 int splash_screen_prepare(void)
 286 {
 287         return splash_source_load(default_splash_locations,
 288                                   ARRAY_SIZE(default_splash_locations));
 289 }
 290 #endif
 291
 292 int board_late_init(void)
 293 {
 294 #if defined(CONFIG_VIDEO_IPUV3)
 295         struct udevice *dev;
 296         int xpos, ypos, ret;
 297         char *s;
 298         void *dst;
 299         ulong addr, len;
 300
 301         splash_get_pos(&xpos, &ypos);
 302
 303         s = env_get("splashimage");
 304         if (!s)
 305                 return 0;
 306
 307         addr = simple_strtoul(s, NULL, 16);
 308         dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
 309         if (!dst)
 310                 return -ENOMEM;
 311
 312         ret = splash_screen_prepare();
 313         if (ret < 0)
 314                 return ret;
 315
 316         len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
 317         ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
 318                      (uchar *)addr, &len);
 319         if (ret) {
 320                 printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
 321                 free(dst);
 322                 return ret;
 323         }
 324
 325         ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
 326         if (ret)
 327                 return ret;
 328
 329         ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
 330         if (ret)
 331                 return ret;
 332 #endif
 333         return 0;
 334 }
 335
 336 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 337                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 338
 339 static void setup_iomux_i2c(void)
 340 {
 341         static const iomux_v3_cfg_t i2c_pads[] = {
 342                 /* I2C1 */
 343                 NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
 344                 NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
 345                 /* I2C2 */
 346                 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
 347                 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
 348         };
 349
 350         imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 351 }
 352
 353 static void setup_iomux_video(void)
 354 {
 355         static const iomux_v3_cfg_t lcd_pads[] = {
 356                 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 357                 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 358                 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 359                 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 360                 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 361         };
 362
 363         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 364 }
 365
 366 static void setup_iomux_nand(void)
 367 {
 368         static const iomux_v3_cfg_t nand_pads[] = {
 369                 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
 370                              PAD_CTL_DSE_HIGH),
 371                 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
 372                              PAD_CTL_DSE_HIGH),
 373                 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
 374                              PAD_CTL_DSE_HIGH),
 375                 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
 376                              PAD_CTL_DSE_HIGH),
 377                 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
 378                              PAD_CTL_PUS_100K_UP),
 379                 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
 380                              PAD_CTL_PUS_100K_UP),
 381                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
 382                              PAD_CTL_DSE_HIGH),
 383                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
 384                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 385                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
 386                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 387                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
 388                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 389                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
 390                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 391                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
 392                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 393                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
 394                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 395                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
 396                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 397                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
 398                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 399         };
 400
 401         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 402 }
 403
 404 static void m53_set_clock(void)
 405 {
 406         int ret;
 407         const u32 ref_clk = MXC_HCLK;
 408         const u32 dramclk = 400;
 409         u32 cpuclk;
 410
 411         gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
 412
 413         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
 414                                             PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
 415         gpio_direction_input(IMX_GPIO_NR(4, 0));
 416
 417         /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
 418         cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
 419
 420         ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
 421         if (ret)
 422                 printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
 423
 424         ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
 425         if (ret) {
 426                 printf("CPU:   Switch peripheral clock to %dMHz failed\n",
 427                        dramclk);
 428         }
 429
 430         ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
 431         if (ret)
 432                 printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
 433 }
 434
 435 static void m53_set_nand(void)
 436 {
 437         u32 i;
 438
 439         /* NAND flash is muxed on ATA pins */
 440         setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
 441
 442         /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
 443         for (i = 0x4; i < 0x94; i += 0x18) {
 444                 clrbits_le32(WEIM_BASE_ADDR + i,
 445                              WEIM_GCR2_MUX16_BYP_GRANT_MASK);
 446         }
 447
 448         mxc_set_clock(0, 33, MXC_NFC_CLK);
 449         enable_nfc_clk(1);
 450 }
 451
 452 int board_early_init_f(void)
 453 {
 454         setup_iomux_uart();
 455         setup_iomux_fec();
 456         setup_iomux_i2c();
 457         setup_iomux_nand();
 458         setup_iomux_video();
 459
 460         m53_set_clock();
 461
 462         mxc_set_sata_internal_clock();
 463
 464         /* NAND clock @ 33MHz */
 465         m53_set_nand();
 466
 467         return 0;
 468 }
 469
 470 int board_init(void)
 471 {
 472         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 473
 474         return 0;
 475 }
 476
 477 int checkboard(void)
 478 {
 479         puts("Board: Menlosystems M53Menlo\n");
 480
 481         return 0;
 482 }
 483
 484 /*
 485  * NAND SPL
 486  */
 487 #ifdef CONFIG_SPL_BUILD
 488 void spl_board_init(void)
 489 {
 490         setup_iomux_nand();
 491         m53_set_clock();
 492         m53_set_nand();
 493 }
 494
 495 u32 spl_boot_device(void)
 496 {
 497         return BOOT_DEVICE_NAND;
 498 }
 499 #endif