board/menlo/m53menlo/m53menlo.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Menlosystems M53Menlo board
   4  *
   5  * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
   6  * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/iomux-mx53.h>
  17 #include <asm/mach-imx/mx5_video.h>
  18 #include <asm/mach-imx/video.h>
  19 #include <asm/gpio.h>
  20 #include <asm/spl.h>
  21 #include <fdt_support.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <i2c.h>
  24 #include <ipu_pixfmt.h>
  25 #include <linux/errno.h>
  26 #include <linux/fb.h>
  27 #include <mmc.h>
  28 #include <netdev.h>
  29 #include <spl.h>
  30 #include <splash.h>
  31 #include <usb/ehci-ci.h>
  32 #include <video_console.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 static u32 mx53_dram_size[2];
  37
  38 ulong board_get_usable_ram_top(ulong total_size)
  39 {
  40         /*
  41          * WARNING: We must override get_effective_memsize() function here
  42          * to report only the size of the first DRAM bank. This is to make
  43          * U-Boot relocator place U-Boot into valid memory, that is, at the
  44          * end of the first DRAM bank. If we did not override this function
  45          * like so, U-Boot would be placed at the address of the first DRAM
  46          * bank + total DRAM size - sizeof(uboot), which in the setup where
  47          * each DRAM bank contains 512MiB of DRAM would result in placing
  48          * U-Boot into invalid memory area close to the end of the first
  49          * DRAM bank.
  50          */
  51         return PHYS_SDRAM_2 + mx53_dram_size[1];
  52 }
  53
  54 int dram_init(void)
  55 {
  56         mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
  57         mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
  58
  59         gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
  60
  61         return 0;
  62 }
  63
  64 int dram_init_banksize(void)
  65 {
  66         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  67         gd->bd->bi_dram[0].size = mx53_dram_size[0];
  68
  69         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  70         gd->bd->bi_dram[1].size = mx53_dram_size[1];
  71
  72         return 0;
  73 }
  74
  75 static void setup_iomux_uart(void)
  76 {
  77         static const iomux_v3_cfg_t uart_pads[] = {
  78                 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  79                 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  80         };
  81
  82         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  83 }
  84
  85 static void setup_iomux_fec(void)
  86 {
  87         static const iomux_v3_cfg_t fec_pads[] = {
  88                 /* MDIO pads */
  89                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  90                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  91                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  92
  93                 /* FEC 0 pads */
  94                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  95                              PAD_CTL_HYS | PAD_CTL_PKE),
  96                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  97                              PAD_CTL_HYS | PAD_CTL_PKE),
  98                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  99                              PAD_CTL_HYS | PAD_CTL_PKE),
 100                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
 101                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 102                              PAD_CTL_HYS | PAD_CTL_PKE),
 103                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 104                              PAD_CTL_HYS | PAD_CTL_PKE),
 105                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 106                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 107
 108                 /* FEC 1 pads */
 109                 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
 110                              PAD_CTL_HYS | PAD_CTL_PKE),
 111                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
 112                              PAD_CTL_HYS | PAD_CTL_PKE),
 113                 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
 114                              PAD_CTL_HYS | PAD_CTL_PKE),
 115                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
 116                              PAD_CTL_HYS | PAD_CTL_PKE),
 117                 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
 118                              PAD_CTL_HYS | PAD_CTL_PKE),
 119                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
 120                 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
 121                              PAD_CTL_HYS | PAD_CTL_PKE),
 122                 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
 123         };
 124
 125         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 126 }
 127
 128 #ifdef CONFIG_FSL_ESDHC_IMX
 129 struct fsl_esdhc_cfg esdhc_cfg = {
 130         MMC_SDHC1_BASE_ADDR,
 131 };
 132
 133 int board_mmc_getcd(struct mmc *mmc)
 134 {
 135         imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
 136         gpio_direction_input(IMX_GPIO_NR(1, 1));
 137
 138         return !gpio_get_value(IMX_GPIO_NR(1, 1));
 139 }
 140
 141 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 142                                  PAD_CTL_PUS_100K_UP)
 143 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 144                                  PAD_CTL_DSE_HIGH)
 145
 146 int board_mmc_init(bd_t *bis)
 147 {
 148         static const iomux_v3_cfg_t sd1_pads[] = {
 149                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 150                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 151                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 152                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 153                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 154                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 155         };
 156
 157         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 158
 159         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 160
 161         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 162 }
 163 #endif
 164
 165 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
 166 {
 167         static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 168         int ret;
 169
 170         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 171         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 172
 173         /*
 174          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 175          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 176          */
 177         ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
 178         if (ret)
 179                 puts("IPU:   Failed to configure LDB clock\n");
 180
 181         /* Configure CCM_CSCMR2 */
 182         clrsetbits_le32(&mxc_ccm->cscmr2,
 183                         (0x7 << 26) | BIT(10) | BIT(8),
 184                         (0x5 << 26) | BIT(10) | BIT(8));
 185
 186         /* Configure LDB_CTRL */
 187         writel(0x201, 0x53fa8008);
 188 }
 189
 190 static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
 191 {
 192         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 193
 194         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 195         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 196
 197         /*
 198          * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
 199          * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 200          */
 201         enable_lvds_clock(dev, 63);
 202 }
 203
 204 static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
 205 {
 206         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 207
 208         /*
 209          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 210          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 211          */
 212         enable_lvds_clock(dev, 233);
 213
 214         /* For ETM0700G0DH6 model, this may be enabled after the clock. */
 215         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 216 }
 217
 218 static const char *lvds_compat_string;
 219
 220 static int detect_lvds(struct display_info_t const *dev)
 221 {
 222         u8 touchid[23];
 223         u8 *touchptr = &touchid[0];
 224         int ret;
 225
 226         ret = i2c_set_bus_num(0);
 227         if (ret)
 228                 return 0;
 229
 230         /* Touchscreen is at address 0x38, ID register is 0xbb. */
 231         ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
 232         if (ret)
 233                 return 0;
 234
 235         /* EP0430 prefixes the response with 0xbb, skip it. */
 236         if (*touchptr == 0xbb)
 237                 touchptr++;
 238
 239         /* Skip the 'EP' prefix. */
 240         touchptr += 2;
 241
 242         ret = !memcmp(touchptr, &dev->mode.name[7], 4);
 243         if (ret)
 244                 lvds_compat_string = dev->mode.name;
 245
 246         return ret;
 247 }
 248
 249 void board_preboot_os(void)
 250 {
 251         /* Power off the LCD to prevent awful color flicker */
 252         gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
 253 }
 254
 255 int ft_board_setup(void *blob, bd_t *bd)
 256 {
 257         if (lvds_compat_string)
 258                 do_fixup_by_path_string(blob, "/panel", "compatible",
 259                                         lvds_compat_string);
 260
 261         return 0;
 262 }
 263
 264 struct display_info_t const displays[] = {
 265         {
 266                 .bus    = 0,
 267                 .addr   = 0,
 268                 .detect = detect_lvds,
 269                 .enable = enable_lvds_etm0430g0dh6,
 270                 .pixfmt = IPU_PIX_FMT_RGB666,
 271                 .mode   = {
 272                         .name           = "edt,etm0430g0dh6",
 273                         .refresh        = 60,
 274                         .xres           = 480,
 275                         .yres           = 272,
 276                         .pixclock       = 111111, /* picosecond (9 MHz) */
 277                         .left_margin    = 2,
 278                         .right_margin   = 2,
 279                         .upper_margin   = 2,
 280                         .lower_margin   = 2,
 281                         .hsync_len      = 41,
 282                         .vsync_len      = 10,
 283                         .sync           = 0x40000000,
 284                         .vmode          = FB_VMODE_NONINTERLACED
 285                 }
 286         }, {
 287                 .bus    = 0,
 288                 .addr   = 0,
 289                 .detect = detect_lvds,
 290                 .enable = enable_lvds_etm0700g0dh6,
 291                 .pixfmt = IPU_PIX_FMT_RGB666,
 292                 .mode   = {
 293                         .name           = "edt,etm0700g0dh6",
 294                         .refresh        = 60,
 295                         .xres           = 800,
 296                         .yres           = 480,
 297                         .pixclock       = 30048, /* picosecond (33.28 MHz) */
 298                         .left_margin    = 40,
 299                         .right_margin   = 88,
 300                         .upper_margin   = 10,
 301                         .lower_margin   = 33,
 302                         .hsync_len      = 128,
 303                         .vsync_len      = 2,
 304                         .sync           = FB_SYNC_EXT,
 305                         .vmode          = FB_VMODE_NONINTERLACED
 306                 }
 307         }
 308 };
 309
 310 size_t display_count = ARRAY_SIZE(displays);
 311
 312 #ifdef CONFIG_SPLASH_SCREEN
 313 static struct splash_location default_splash_locations[] = {
 314         {
 315                 .name           = "mmc_fs",
 316                 .storage        = SPLASH_STORAGE_MMC,
 317                 .flags          = SPLASH_STORAGE_FS,
 318                 .devpart        = "0:1",
 319         },
 320 };
 321
 322 int splash_screen_prepare(void)
 323 {
 324         return splash_source_load(default_splash_locations,
 325                                   ARRAY_SIZE(default_splash_locations));
 326 }
 327 #endif
 328
 329 int board_late_init(void)
 330 {
 331 #if defined(CONFIG_VIDEO_IPUV3)
 332         struct udevice *dev;
 333         int xpos, ypos, ret;
 334         char *s;
 335         void *dst;
 336         ulong addr, len;
 337
 338         splash_get_pos(&xpos, &ypos);
 339
 340         s = env_get("splashimage");
 341         if (!s)
 342                 return 0;
 343
 344         addr = simple_strtoul(s, NULL, 16);
 345         dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
 346         if (!dst)
 347                 return -ENOMEM;
 348
 349         ret = splash_screen_prepare();
 350         if (ret < 0)
 351                 return ret;
 352
 353         len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
 354         ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
 355                      (uchar *)addr, &len);
 356         if (ret) {
 357                 printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
 358                 free(dst);
 359                 return ret;
 360         }
 361
 362         ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
 363         if (ret)
 364                 return ret;
 365
 366         ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
 367         if (ret)
 368                 return ret;
 369 #endif
 370         return 0;
 371 }
 372
 373 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 374                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 375
 376 static void setup_iomux_i2c(void)
 377 {
 378         static const iomux_v3_cfg_t i2c_pads[] = {
 379                 /* I2C1 */
 380                 NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
 381                 NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
 382                 /* I2C2 */
 383                 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
 384                 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
 385         };
 386
 387         imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 388 }
 389
 390 static void setup_iomux_video(void)
 391 {
 392         static const iomux_v3_cfg_t lcd_pads[] = {
 393                 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 394                 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 395                 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 396                 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 397                 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 398         };
 399
 400         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 401 }
 402
 403 static void setup_iomux_nand(void)
 404 {
 405         static const iomux_v3_cfg_t nand_pads[] = {
 406                 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
 407                              PAD_CTL_DSE_HIGH),
 408                 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
 409                              PAD_CTL_DSE_HIGH),
 410                 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
 411                              PAD_CTL_DSE_HIGH),
 412                 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
 413                              PAD_CTL_DSE_HIGH),
 414                 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
 415                              PAD_CTL_PUS_100K_UP),
 416                 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
 417                              PAD_CTL_PUS_100K_UP),
 418                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
 419                              PAD_CTL_DSE_HIGH),
 420                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
 421                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 422                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
 423                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 424                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
 425                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 426                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
 427                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 428                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
 429                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 430                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
 431                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 432                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
 433                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 434                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
 435                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 436         };
 437
 438         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 439 }
 440
 441 static void m53_set_clock(void)
 442 {
 443         int ret;
 444         const u32 ref_clk = MXC_HCLK;
 445         const u32 dramclk = 400;
 446         u32 cpuclk;
 447
 448         gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
 449
 450         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
 451                                             PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
 452         gpio_direction_input(IMX_GPIO_NR(4, 0));
 453
 454         /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
 455         cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
 456
 457         ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
 458         if (ret)
 459                 printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
 460
 461         ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
 462         if (ret) {
 463                 printf("CPU:   Switch peripheral clock to %dMHz failed\n",
 464                        dramclk);
 465         }
 466
 467         ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
 468         if (ret)
 469                 printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
 470 }
 471
 472 static void m53_set_nand(void)
 473 {
 474         u32 i;
 475
 476         /* NAND flash is muxed on ATA pins */
 477         setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
 478
 479         /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
 480         for (i = 0x4; i < 0x94; i += 0x18) {
 481                 clrbits_le32(WEIM_BASE_ADDR + i,
 482                              WEIM_GCR2_MUX16_BYP_GRANT_MASK);
 483         }
 484
 485         mxc_set_clock(0, 33, MXC_NFC_CLK);
 486         enable_nfc_clk(1);
 487 }
 488
 489 int board_early_init_f(void)
 490 {
 491         setup_iomux_uart();
 492         setup_iomux_fec();
 493         setup_iomux_i2c();
 494         setup_iomux_nand();
 495         setup_iomux_video();
 496
 497         m53_set_clock();
 498
 499         mxc_set_sata_internal_clock();
 500
 501         /* NAND clock @ 33MHz */
 502         m53_set_nand();
 503
 504         return 0;
 505 }
 506
 507 int board_init(void)
 508 {
 509         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 510
 511         return 0;
 512 }
 513
 514 int checkboard(void)
 515 {
 516         puts("Board: Menlosystems M53Menlo\n");
 517
 518         return 0;
 519 }
 520
 521 /*
 522  * NAND SPL
 523  */
 524 #ifdef CONFIG_SPL_BUILD
 525 void spl_board_init(void)
 526 {
 527         setup_iomux_nand();
 528         m53_set_clock();
 529         m53_set_nand();
 530 }
 531
 532 u32 spl_boot_device(void)
 533 {
 534         return BOOT_DEVICE_NAND;
 535 }
 536 #endif