board/menlo/m53menlo/m53menlo.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Menlosystems M53Menlo board
   4  *
   5  * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
   6  * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <init.h>
  12 #include <malloc.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/iomux-mx53.h>
  19 #include <asm/mach-imx/mx5_video.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <asm/gpio.h>
  22 #include <asm/spl.h>
  23 #include <env.h>
  24 #include <fdt_support.h>
  25 #include <fsl_esdhc_imx.h>
  26 #include <gzip.h>
  27 #include <i2c.h>
  28 #include <ipu_pixfmt.h>
  29 #include <linux/bitops.h>
  30 #include <linux/errno.h>
  31 #include <linux/fb.h>
  32 #include <mmc.h>
  33 #include <netdev.h>
  34 #include <spl.h>
  35 #include <splash.h>
  36 #include <usb/ehci-ci.h>
  37 #include <video_console.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 static u32 mx53_dram_size[2];
  42
  43 ulong board_get_usable_ram_top(ulong total_size)
  44 {
  45         /*
  46          * WARNING: We must override get_effective_memsize() function here
  47          * to report only the size of the first DRAM bank. This is to make
  48          * U-Boot relocator place U-Boot into valid memory, that is, at the
  49          * end of the first DRAM bank. If we did not override this function
  50          * like so, U-Boot would be placed at the address of the first DRAM
  51          * bank + total DRAM size - sizeof(uboot), which in the setup where
  52          * each DRAM bank contains 512MiB of DRAM would result in placing
  53          * U-Boot into invalid memory area close to the end of the first
  54          * DRAM bank.
  55          */
  56         return PHYS_SDRAM_2 + mx53_dram_size[1];
  57 }
  58
  59 int dram_init(void)
  60 {
  61         mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
  62         mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
  63
  64         gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
  65
  66         return 0;
  67 }
  68
  69 int dram_init_banksize(void)
  70 {
  71         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  72         gd->bd->bi_dram[0].size = mx53_dram_size[0];
  73
  74         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  75         gd->bd->bi_dram[1].size = mx53_dram_size[1];
  76
  77         return 0;
  78 }
  79
  80 static void setup_iomux_uart(void)
  81 {
  82         static const iomux_v3_cfg_t uart_pads[] = {
  83                 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  84                 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  85         };
  86
  87         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  88 }
  89
  90 static void setup_iomux_fec(void)
  91 {
  92         static const iomux_v3_cfg_t fec_pads[] = {
  93                 /* MDIO pads */
  94                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  95                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  96                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  97
  98                 /* FEC 0 pads */
  99                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 100                              PAD_CTL_HYS | PAD_CTL_PKE),
 101                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
 102                              PAD_CTL_HYS | PAD_CTL_PKE),
 103                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 104                              PAD_CTL_HYS | PAD_CTL_PKE),
 105                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
 106                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 107                              PAD_CTL_HYS | PAD_CTL_PKE),
 108                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 109                              PAD_CTL_HYS | PAD_CTL_PKE),
 110                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 111                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 112
 113                 /* FEC 1 pads */
 114                 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
 115                              PAD_CTL_HYS | PAD_CTL_PKE),
 116                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
 117                              PAD_CTL_HYS | PAD_CTL_PKE),
 118                 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
 119                              PAD_CTL_HYS | PAD_CTL_PKE),
 120                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
 121                              PAD_CTL_HYS | PAD_CTL_PKE),
 122                 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
 123                              PAD_CTL_HYS | PAD_CTL_PKE),
 124                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
 125                 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
 126                              PAD_CTL_HYS | PAD_CTL_PKE),
 127                 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
 128         };
 129
 130         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 131 }
 132
 133 #ifdef CONFIG_FSL_ESDHC_IMX
 134 struct fsl_esdhc_cfg esdhc_cfg = {
 135         MMC_SDHC1_BASE_ADDR,
 136 };
 137
 138 int board_mmc_getcd(struct mmc *mmc)
 139 {
 140         imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
 141         gpio_direction_input(IMX_GPIO_NR(1, 1));
 142
 143         return !gpio_get_value(IMX_GPIO_NR(1, 1));
 144 }
 145
 146 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 147                                  PAD_CTL_PUS_100K_UP)
 148 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 149                                  PAD_CTL_DSE_HIGH)
 150
 151 int board_mmc_init(bd_t *bis)
 152 {
 153         static const iomux_v3_cfg_t sd1_pads[] = {
 154                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 155                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 156                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 157                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 158                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 159                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 160         };
 161
 162         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 163
 164         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 165
 166         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 167 }
 168 #endif
 169
 170 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
 171 {
 172         static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 173         int ret;
 174
 175         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 176         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 177
 178         /*
 179          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 180          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 181          */
 182         ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
 183         if (ret)
 184                 puts("IPU:   Failed to configure LDB clock\n");
 185
 186         /* Configure CCM_CSCMR2 */
 187         clrsetbits_le32(&mxc_ccm->cscmr2,
 188                         (0x7 << 26) | BIT(10) | BIT(8),
 189                         (0x5 << 26) | BIT(10) | BIT(8));
 190
 191         /* Configure LDB_CTRL */
 192         writel(0x201, 0x53fa8008);
 193 }
 194
 195 static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
 196 {
 197         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 198
 199         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 200         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 201
 202         /*
 203          * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
 204          * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 205          */
 206         enable_lvds_clock(dev, 63);
 207 }
 208
 209 static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
 210 {
 211         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 212
 213         /*
 214          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 215          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 216          */
 217         enable_lvds_clock(dev, 233);
 218
 219         /* For ETM0700G0DH6 model, this may be enabled after the clock. */
 220         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 221 }
 222
 223 static const char *lvds_compat_string;
 224
 225 static int detect_lvds(struct display_info_t const *dev)
 226 {
 227         u8 touchid[23];
 228         u8 *touchptr = &touchid[0];
 229         int ret;
 230
 231         ret = i2c_set_bus_num(0);
 232         if (ret)
 233                 return 0;
 234
 235         /* Touchscreen is at address 0x38, ID register is 0xbb. */
 236         ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
 237         if (ret)
 238                 return 0;
 239
 240         /* EP0430 prefixes the response with 0xbb, skip it. */
 241         if (*touchptr == 0xbb)
 242                 touchptr++;
 243
 244         /* Skip the 'EP' prefix. */
 245         touchptr += 2;
 246
 247         ret = !memcmp(touchptr, &dev->mode.name[7], 4);
 248         if (ret)
 249                 lvds_compat_string = dev->mode.name;
 250
 251         return ret;
 252 }
 253
 254 void board_preboot_os(void)
 255 {
 256         /* Power off the LCD to prevent awful color flicker */
 257         gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
 258 }
 259
 260 int ft_board_setup(void *blob, bd_t *bd)
 261 {
 262         if (lvds_compat_string)
 263                 do_fixup_by_path_string(blob, "/panel", "compatible",
 264                                         lvds_compat_string);
 265
 266         return 0;
 267 }
 268
 269 struct display_info_t const displays[] = {
 270         {
 271                 .bus    = 0,
 272                 .addr   = 0,
 273                 .detect = detect_lvds,
 274                 .enable = enable_lvds_etm0430g0dh6,
 275                 .pixfmt = IPU_PIX_FMT_RGB666,
 276                 .mode   = {
 277                         .name           = "edt,etm0430g0dh6",
 278                         .refresh        = 60,
 279                         .xres           = 480,
 280                         .yres           = 272,
 281                         .pixclock       = 111111, /* picosecond (9 MHz) */
 282                         .left_margin    = 2,
 283                         .right_margin   = 2,
 284                         .upper_margin   = 2,
 285                         .lower_margin   = 2,
 286                         .hsync_len      = 41,
 287                         .vsync_len      = 10,
 288                         .sync           = 0x40000000,
 289                         .vmode          = FB_VMODE_NONINTERLACED
 290                 }
 291         }, {
 292                 .bus    = 0,
 293                 .addr   = 0,
 294                 .detect = detect_lvds,
 295                 .enable = enable_lvds_etm0700g0dh6,
 296                 .pixfmt = IPU_PIX_FMT_RGB666,
 297                 .mode   = {
 298                         .name           = "edt,etm0700g0dh6",
 299                         .refresh        = 60,
 300                         .xres           = 800,
 301                         .yres           = 480,
 302                         .pixclock       = 30048, /* picosecond (33.28 MHz) */
 303                         .left_margin    = 40,
 304                         .right_margin   = 88,
 305                         .upper_margin   = 10,
 306                         .lower_margin   = 33,
 307                         .hsync_len      = 128,
 308                         .vsync_len      = 2,
 309                         .sync           = FB_SYNC_EXT,
 310                         .vmode          = FB_VMODE_NONINTERLACED
 311                 }
 312         }
 313 };
 314
 315 size_t display_count = ARRAY_SIZE(displays);
 316
 317 #ifdef CONFIG_SPLASH_SCREEN
 318 static struct splash_location default_splash_locations[] = {
 319         {
 320                 .name           = "mmc_fs",
 321                 .storage        = SPLASH_STORAGE_MMC,
 322                 .flags          = SPLASH_STORAGE_FS,
 323                 .devpart        = "0:1",
 324         },
 325 };
 326
 327 int splash_screen_prepare(void)
 328 {
 329         return splash_source_load(default_splash_locations,
 330                                   ARRAY_SIZE(default_splash_locations));
 331 }
 332 #endif
 333
 334 int board_late_init(void)
 335 {
 336 #if defined(CONFIG_VIDEO_IPUV3)
 337         struct udevice *dev;
 338         int xpos, ypos, ret;
 339         char *s;
 340         void *dst;
 341         ulong addr, len;
 342
 343         splash_get_pos(&xpos, &ypos);
 344
 345         s = env_get("splashimage");
 346         if (!s)
 347                 return 0;
 348
 349         addr = simple_strtoul(s, NULL, 16);
 350         dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
 351         if (!dst)
 352                 return -ENOMEM;
 353
 354         ret = splash_screen_prepare();
 355         if (ret < 0)
 356                 goto splasherr;
 357
 358         len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
 359         ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
 360                      (uchar *)addr, &len);
 361         if (ret) {
 362                 printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
 363                 goto splasherr;
 364         }
 365
 366         ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
 367         if (ret)
 368                 goto splasherr;
 369
 370         ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
 371         if (ret)
 372                 goto splasherr;
 373
 374         return 0;
 375
 376 splasherr:
 377         free(dst);
 378 #endif
 379         return 0;
 380 }
 381
 382 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 383                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 384
 385 static void setup_iomux_i2c(void)
 386 {
 387         static const iomux_v3_cfg_t i2c_pads[] = {
 388                 /* I2C1 */
 389                 NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
 390                 NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
 391                 /* I2C2 */
 392                 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
 393                 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
 394         };
 395
 396         imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 397 }
 398
 399 static void setup_iomux_video(void)
 400 {
 401         static const iomux_v3_cfg_t lcd_pads[] = {
 402                 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 403                 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 404                 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 405                 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 406                 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 407         };
 408
 409         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 410 }
 411
 412 static void setup_iomux_nand(void)
 413 {
 414         static const iomux_v3_cfg_t nand_pads[] = {
 415                 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
 416                              PAD_CTL_DSE_HIGH),
 417                 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
 418                              PAD_CTL_DSE_HIGH),
 419                 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
 420                              PAD_CTL_DSE_HIGH),
 421                 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
 422                              PAD_CTL_DSE_HIGH),
 423                 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
 424                              PAD_CTL_PUS_100K_UP),
 425                 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
 426                              PAD_CTL_PUS_100K_UP),
 427                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
 428                              PAD_CTL_DSE_HIGH),
 429                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
 430                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 431                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
 432                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 433                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
 434                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 435                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
 436                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 437                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
 438                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 439                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
 440                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 441                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
 442                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 443                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
 444                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 445         };
 446
 447         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 448 }
 449
 450 static void m53_set_clock(void)
 451 {
 452         int ret;
 453         const u32 ref_clk = MXC_HCLK;
 454         const u32 dramclk = 400;
 455         u32 cpuclk;
 456
 457         gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
 458
 459         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
 460                                             PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
 461         gpio_direction_input(IMX_GPIO_NR(4, 0));
 462
 463         /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
 464         cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
 465
 466         ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
 467         if (ret)
 468                 printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
 469
 470         ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
 471         if (ret) {
 472                 printf("CPU:   Switch peripheral clock to %dMHz failed\n",
 473                        dramclk);
 474         }
 475
 476         ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
 477         if (ret)
 478                 printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
 479 }
 480
 481 static void m53_set_nand(void)
 482 {
 483         u32 i;
 484
 485         /* NAND flash is muxed on ATA pins */
 486         setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
 487
 488         /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
 489         for (i = 0x4; i < 0x94; i += 0x18) {
 490                 clrbits_le32(WEIM_BASE_ADDR + i,
 491                              WEIM_GCR2_MUX16_BYP_GRANT_MASK);
 492         }
 493
 494         mxc_set_clock(0, 33, MXC_NFC_CLK);
 495         enable_nfc_clk(1);
 496 }
 497
 498 int board_early_init_f(void)
 499 {
 500         setup_iomux_uart();
 501         setup_iomux_fec();
 502         setup_iomux_i2c();
 503         setup_iomux_nand();
 504         setup_iomux_video();
 505
 506         m53_set_clock();
 507
 508         mxc_set_sata_internal_clock();
 509
 510         /* NAND clock @ 33MHz */
 511         m53_set_nand();
 512
 513         return 0;
 514 }
 515
 516 int board_init(void)
 517 {
 518         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 519
 520         return 0;
 521 }
 522
 523 int checkboard(void)
 524 {
 525         puts("Board: Menlosystems M53Menlo\n");
 526
 527         return 0;
 528 }
 529
 530 /*
 531  * NAND SPL
 532  */
 533 #ifdef CONFIG_SPL_BUILD
 534 void spl_board_init(void)
 535 {
 536         setup_iomux_nand();
 537         m53_set_clock();
 538         m53_set_nand();
 539 }
 540
 541 u32 spl_boot_device(void)
 542 {
 543         return BOOT_DEVICE_NAND;
 544 }
 545 #endif