board/menlo/m53menlo/m53menlo.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Menlosystems M53Menlo board
   4  *
   5  * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
   6  * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <init.h>
  12 #include <malloc.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/iomux-mx53.h>
  19 #include <asm/mach-imx/mx5_video.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <asm/gpio.h>
  22 #include <asm/spl.h>
  23 #include <env.h>
  24 #include <fdt_support.h>
  25 #include <fsl_esdhc_imx.h>
  26 #include <gzip.h>
  27 #include <i2c.h>
  28 #include <ipu_pixfmt.h>
  29 #include <linux/errno.h>
  30 #include <linux/fb.h>
  31 #include <mmc.h>
  32 #include <netdev.h>
  33 #include <spl.h>
  34 #include <splash.h>
  35 #include <usb/ehci-ci.h>
  36 #include <video_console.h>
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 static u32 mx53_dram_size[2];
  41
  42 ulong board_get_usable_ram_top(ulong total_size)
  43 {
  44         /*
  45          * WARNING: We must override get_effective_memsize() function here
  46          * to report only the size of the first DRAM bank. This is to make
  47          * U-Boot relocator place U-Boot into valid memory, that is, at the
  48          * end of the first DRAM bank. If we did not override this function
  49          * like so, U-Boot would be placed at the address of the first DRAM
  50          * bank + total DRAM size - sizeof(uboot), which in the setup where
  51          * each DRAM bank contains 512MiB of DRAM would result in placing
  52          * U-Boot into invalid memory area close to the end of the first
  53          * DRAM bank.
  54          */
  55         return PHYS_SDRAM_2 + mx53_dram_size[1];
  56 }
  57
  58 int dram_init(void)
  59 {
  60         mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
  61         mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
  62
  63         gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
  64
  65         return 0;
  66 }
  67
  68 int dram_init_banksize(void)
  69 {
  70         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  71         gd->bd->bi_dram[0].size = mx53_dram_size[0];
  72
  73         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  74         gd->bd->bi_dram[1].size = mx53_dram_size[1];
  75
  76         return 0;
  77 }
  78
  79 static void setup_iomux_uart(void)
  80 {
  81         static const iomux_v3_cfg_t uart_pads[] = {
  82                 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  83                 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  84         };
  85
  86         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  87 }
  88
  89 static void setup_iomux_fec(void)
  90 {
  91         static const iomux_v3_cfg_t fec_pads[] = {
  92                 /* MDIO pads */
  93                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  94                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  95                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  96
  97                 /* FEC 0 pads */
  98                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  99                              PAD_CTL_HYS | PAD_CTL_PKE),
 100                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
 101                              PAD_CTL_HYS | PAD_CTL_PKE),
 102                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 103                              PAD_CTL_HYS | PAD_CTL_PKE),
 104                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
 105                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 106                              PAD_CTL_HYS | PAD_CTL_PKE),
 107                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 108                              PAD_CTL_HYS | PAD_CTL_PKE),
 109                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 110                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 111
 112                 /* FEC 1 pads */
 113                 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
 114                              PAD_CTL_HYS | PAD_CTL_PKE),
 115                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
 116                              PAD_CTL_HYS | PAD_CTL_PKE),
 117                 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
 118                              PAD_CTL_HYS | PAD_CTL_PKE),
 119                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
 120                              PAD_CTL_HYS | PAD_CTL_PKE),
 121                 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
 122                              PAD_CTL_HYS | PAD_CTL_PKE),
 123                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
 124                 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
 125                              PAD_CTL_HYS | PAD_CTL_PKE),
 126                 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
 127         };
 128
 129         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 130 }
 131
 132 #ifdef CONFIG_FSL_ESDHC_IMX
 133 struct fsl_esdhc_cfg esdhc_cfg = {
 134         MMC_SDHC1_BASE_ADDR,
 135 };
 136
 137 int board_mmc_getcd(struct mmc *mmc)
 138 {
 139         imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
 140         gpio_direction_input(IMX_GPIO_NR(1, 1));
 141
 142         return !gpio_get_value(IMX_GPIO_NR(1, 1));
 143 }
 144
 145 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 146                                  PAD_CTL_PUS_100K_UP)
 147 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 148                                  PAD_CTL_DSE_HIGH)
 149
 150 int board_mmc_init(bd_t *bis)
 151 {
 152         static const iomux_v3_cfg_t sd1_pads[] = {
 153                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 154                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 155                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 156                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 157                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 158                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 159         };
 160
 161         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 162
 163         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 164
 165         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 166 }
 167 #endif
 168
 169 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
 170 {
 171         static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 172         int ret;
 173
 174         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 175         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 176
 177         /*
 178          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 179          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 180          */
 181         ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
 182         if (ret)
 183                 puts("IPU:   Failed to configure LDB clock\n");
 184
 185         /* Configure CCM_CSCMR2 */
 186         clrsetbits_le32(&mxc_ccm->cscmr2,
 187                         (0x7 << 26) | BIT(10) | BIT(8),
 188                         (0x5 << 26) | BIT(10) | BIT(8));
 189
 190         /* Configure LDB_CTRL */
 191         writel(0x201, 0x53fa8008);
 192 }
 193
 194 static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
 195 {
 196         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 197
 198         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 199         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 200
 201         /*
 202          * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
 203          * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 204          */
 205         enable_lvds_clock(dev, 63);
 206 }
 207
 208 static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
 209 {
 210         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 211
 212         /*
 213          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 214          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 215          */
 216         enable_lvds_clock(dev, 233);
 217
 218         /* For ETM0700G0DH6 model, this may be enabled after the clock. */
 219         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 220 }
 221
 222 static const char *lvds_compat_string;
 223
 224 static int detect_lvds(struct display_info_t const *dev)
 225 {
 226         u8 touchid[23];
 227         u8 *touchptr = &touchid[0];
 228         int ret;
 229
 230         ret = i2c_set_bus_num(0);
 231         if (ret)
 232                 return 0;
 233
 234         /* Touchscreen is at address 0x38, ID register is 0xbb. */
 235         ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
 236         if (ret)
 237                 return 0;
 238
 239         /* EP0430 prefixes the response with 0xbb, skip it. */
 240         if (*touchptr == 0xbb)
 241                 touchptr++;
 242
 243         /* Skip the 'EP' prefix. */
 244         touchptr += 2;
 245
 246         ret = !memcmp(touchptr, &dev->mode.name[7], 4);
 247         if (ret)
 248                 lvds_compat_string = dev->mode.name;
 249
 250         return ret;
 251 }
 252
 253 void board_preboot_os(void)
 254 {
 255         /* Power off the LCD to prevent awful color flicker */
 256         gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
 257 }
 258
 259 int ft_board_setup(void *blob, bd_t *bd)
 260 {
 261         if (lvds_compat_string)
 262                 do_fixup_by_path_string(blob, "/panel", "compatible",
 263                                         lvds_compat_string);
 264
 265         return 0;
 266 }
 267
 268 struct display_info_t const displays[] = {
 269         {
 270                 .bus    = 0,
 271                 .addr   = 0,
 272                 .detect = detect_lvds,
 273                 .enable = enable_lvds_etm0430g0dh6,
 274                 .pixfmt = IPU_PIX_FMT_RGB666,
 275                 .mode   = {
 276                         .name           = "edt,etm0430g0dh6",
 277                         .refresh        = 60,
 278                         .xres           = 480,
 279                         .yres           = 272,
 280                         .pixclock       = 111111, /* picosecond (9 MHz) */
 281                         .left_margin    = 2,
 282                         .right_margin   = 2,
 283                         .upper_margin   = 2,
 284                         .lower_margin   = 2,
 285                         .hsync_len      = 41,
 286                         .vsync_len      = 10,
 287                         .sync           = 0x40000000,
 288                         .vmode          = FB_VMODE_NONINTERLACED
 289                 }
 290         }, {
 291                 .bus    = 0,
 292                 .addr   = 0,
 293                 .detect = detect_lvds,
 294                 .enable = enable_lvds_etm0700g0dh6,
 295                 .pixfmt = IPU_PIX_FMT_RGB666,
 296                 .mode   = {
 297                         .name           = "edt,etm0700g0dh6",
 298                         .refresh        = 60,
 299                         .xres           = 800,
 300                         .yres           = 480,
 301                         .pixclock       = 30048, /* picosecond (33.28 MHz) */
 302                         .left_margin    = 40,
 303                         .right_margin   = 88,
 304                         .upper_margin   = 10,
 305                         .lower_margin   = 33,
 306                         .hsync_len      = 128,
 307                         .vsync_len      = 2,
 308                         .sync           = FB_SYNC_EXT,
 309                         .vmode          = FB_VMODE_NONINTERLACED
 310                 }
 311         }
 312 };
 313
 314 size_t display_count = ARRAY_SIZE(displays);
 315
 316 #ifdef CONFIG_SPLASH_SCREEN
 317 static struct splash_location default_splash_locations[] = {
 318         {
 319                 .name           = "mmc_fs",
 320                 .storage        = SPLASH_STORAGE_MMC,
 321                 .flags          = SPLASH_STORAGE_FS,
 322                 .devpart        = "0:1",
 323         },
 324 };
 325
 326 int splash_screen_prepare(void)
 327 {
 328         return splash_source_load(default_splash_locations,
 329                                   ARRAY_SIZE(default_splash_locations));
 330 }
 331 #endif
 332
 333 int board_late_init(void)
 334 {
 335 #if defined(CONFIG_VIDEO_IPUV3)
 336         struct udevice *dev;
 337         int xpos, ypos, ret;
 338         char *s;
 339         void *dst;
 340         ulong addr, len;
 341
 342         splash_get_pos(&xpos, &ypos);
 343
 344         s = env_get("splashimage");
 345         if (!s)
 346                 return 0;
 347
 348         addr = simple_strtoul(s, NULL, 16);
 349         dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
 350         if (!dst)
 351                 return -ENOMEM;
 352
 353         ret = splash_screen_prepare();
 354         if (ret < 0)
 355                 return ret;
 356
 357         len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
 358         ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
 359                      (uchar *)addr, &len);
 360         if (ret) {
 361                 printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
 362                 free(dst);
 363                 return ret;
 364         }
 365
 366         ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
 367         if (ret)
 368                 return ret;
 369
 370         ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
 371         if (ret)
 372                 return ret;
 373 #endif
 374         return 0;
 375 }
 376
 377 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 378                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 379
 380 static void setup_iomux_i2c(void)
 381 {
 382         static const iomux_v3_cfg_t i2c_pads[] = {
 383                 /* I2C1 */
 384                 NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
 385                 NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
 386                 /* I2C2 */
 387                 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
 388                 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
 389         };
 390
 391         imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 392 }
 393
 394 static void setup_iomux_video(void)
 395 {
 396         static const iomux_v3_cfg_t lcd_pads[] = {
 397                 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 398                 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 399                 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 400                 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 401                 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 402         };
 403
 404         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 405 }
 406
 407 static void setup_iomux_nand(void)
 408 {
 409         static const iomux_v3_cfg_t nand_pads[] = {
 410                 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
 411                              PAD_CTL_DSE_HIGH),
 412                 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
 413                              PAD_CTL_DSE_HIGH),
 414                 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
 415                              PAD_CTL_DSE_HIGH),
 416                 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
 417                              PAD_CTL_DSE_HIGH),
 418                 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
 419                              PAD_CTL_PUS_100K_UP),
 420                 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
 421                              PAD_CTL_PUS_100K_UP),
 422                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
 423                              PAD_CTL_DSE_HIGH),
 424                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
 425                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 426                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
 427                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 428                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
 429                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 430                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
 431                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 432                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
 433                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 434                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
 435                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 436                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
 437                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 438                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
 439                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 440         };
 441
 442         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 443 }
 444
 445 static void m53_set_clock(void)
 446 {
 447         int ret;
 448         const u32 ref_clk = MXC_HCLK;
 449         const u32 dramclk = 400;
 450         u32 cpuclk;
 451
 452         gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
 453
 454         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
 455                                             PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
 456         gpio_direction_input(IMX_GPIO_NR(4, 0));
 457
 458         /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
 459         cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
 460
 461         ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
 462         if (ret)
 463                 printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
 464
 465         ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
 466         if (ret) {
 467                 printf("CPU:   Switch peripheral clock to %dMHz failed\n",
 468                        dramclk);
 469         }
 470
 471         ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
 472         if (ret)
 473                 printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
 474 }
 475
 476 static void m53_set_nand(void)
 477 {
 478         u32 i;
 479
 480         /* NAND flash is muxed on ATA pins */
 481         setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
 482
 483         /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
 484         for (i = 0x4; i < 0x94; i += 0x18) {
 485                 clrbits_le32(WEIM_BASE_ADDR + i,
 486                              WEIM_GCR2_MUX16_BYP_GRANT_MASK);
 487         }
 488
 489         mxc_set_clock(0, 33, MXC_NFC_CLK);
 490         enable_nfc_clk(1);
 491 }
 492
 493 int board_early_init_f(void)
 494 {
 495         setup_iomux_uart();
 496         setup_iomux_fec();
 497         setup_iomux_i2c();
 498         setup_iomux_nand();
 499         setup_iomux_video();
 500
 501         m53_set_clock();
 502
 503         mxc_set_sata_internal_clock();
 504
 505         /* NAND clock @ 33MHz */
 506         m53_set_nand();
 507
 508         return 0;
 509 }
 510
 511 int board_init(void)
 512 {
 513         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 514
 515         return 0;
 516 }
 517
 518 int checkboard(void)
 519 {
 520         puts("Board: Menlosystems M53Menlo\n");
 521
 522         return 0;
 523 }
 524
 525 /*
 526  * NAND SPL
 527  */
 528 #ifdef CONFIG_SPL_BUILD
 529 void spl_board_init(void)
 530 {
 531         setup_iomux_nand();
 532         m53_set_clock();
 533         m53_set_nand();
 534 }
 535
 536 u32 spl_boot_device(void)
 537 {
 538         return BOOT_DEVICE_NAND;
 539 }
 540 #endif