board/menlo/m53menlo/m53menlo.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Menlosystems M53Menlo board
   4  *
   5  * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
   6  * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/iomux-mx53.h>
  17 #include <asm/mach-imx/mx5_video.h>
  18 #include <asm/mach-imx/video.h>
  19 #include <asm/gpio.h>
  20 #include <asm/spl.h>
  21 #include <env.h>
  22 #include <fdt_support.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <gzip.h>
  25 #include <i2c.h>
  26 #include <ipu_pixfmt.h>
  27 #include <linux/errno.h>
  28 #include <linux/fb.h>
  29 #include <mmc.h>
  30 #include <netdev.h>
  31 #include <spl.h>
  32 #include <splash.h>
  33 #include <usb/ehci-ci.h>
  34 #include <video_console.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 static u32 mx53_dram_size[2];
  39
  40 ulong board_get_usable_ram_top(ulong total_size)
  41 {
  42         /*
  43          * WARNING: We must override get_effective_memsize() function here
  44          * to report only the size of the first DRAM bank. This is to make
  45          * U-Boot relocator place U-Boot into valid memory, that is, at the
  46          * end of the first DRAM bank. If we did not override this function
  47          * like so, U-Boot would be placed at the address of the first DRAM
  48          * bank + total DRAM size - sizeof(uboot), which in the setup where
  49          * each DRAM bank contains 512MiB of DRAM would result in placing
  50          * U-Boot into invalid memory area close to the end of the first
  51          * DRAM bank.
  52          */
  53         return PHYS_SDRAM_2 + mx53_dram_size[1];
  54 }
  55
  56 int dram_init(void)
  57 {
  58         mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
  59         mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
  60
  61         gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
  62
  63         return 0;
  64 }
  65
  66 int dram_init_banksize(void)
  67 {
  68         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  69         gd->bd->bi_dram[0].size = mx53_dram_size[0];
  70
  71         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  72         gd->bd->bi_dram[1].size = mx53_dram_size[1];
  73
  74         return 0;
  75 }
  76
  77 static void setup_iomux_uart(void)
  78 {
  79         static const iomux_v3_cfg_t uart_pads[] = {
  80                 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  81                 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  82         };
  83
  84         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  85 }
  86
  87 static void setup_iomux_fec(void)
  88 {
  89         static const iomux_v3_cfg_t fec_pads[] = {
  90                 /* MDIO pads */
  91                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  92                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  93                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  94
  95                 /* FEC 0 pads */
  96                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  97                              PAD_CTL_HYS | PAD_CTL_PKE),
  98                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  99                              PAD_CTL_HYS | PAD_CTL_PKE),
 100                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 101                              PAD_CTL_HYS | PAD_CTL_PKE),
 102                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
 103                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 104                              PAD_CTL_HYS | PAD_CTL_PKE),
 105                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 106                              PAD_CTL_HYS | PAD_CTL_PKE),
 107                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 108                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 109
 110                 /* FEC 1 pads */
 111                 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
 112                              PAD_CTL_HYS | PAD_CTL_PKE),
 113                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
 114                              PAD_CTL_HYS | PAD_CTL_PKE),
 115                 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
 116                              PAD_CTL_HYS | PAD_CTL_PKE),
 117                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
 118                              PAD_CTL_HYS | PAD_CTL_PKE),
 119                 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
 120                              PAD_CTL_HYS | PAD_CTL_PKE),
 121                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
 122                 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
 123                              PAD_CTL_HYS | PAD_CTL_PKE),
 124                 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
 125         };
 126
 127         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 128 }
 129
 130 #ifdef CONFIG_FSL_ESDHC_IMX
 131 struct fsl_esdhc_cfg esdhc_cfg = {
 132         MMC_SDHC1_BASE_ADDR,
 133 };
 134
 135 int board_mmc_getcd(struct mmc *mmc)
 136 {
 137         imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
 138         gpio_direction_input(IMX_GPIO_NR(1, 1));
 139
 140         return !gpio_get_value(IMX_GPIO_NR(1, 1));
 141 }
 142
 143 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 144                                  PAD_CTL_PUS_100K_UP)
 145 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 146                                  PAD_CTL_DSE_HIGH)
 147
 148 int board_mmc_init(bd_t *bis)
 149 {
 150         static const iomux_v3_cfg_t sd1_pads[] = {
 151                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 152                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 153                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 154                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 155                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 156                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 157         };
 158
 159         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 160
 161         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 162
 163         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 164 }
 165 #endif
 166
 167 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
 168 {
 169         static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 170         int ret;
 171
 172         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 173         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 174
 175         /*
 176          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 177          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 178          */
 179         ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
 180         if (ret)
 181                 puts("IPU:   Failed to configure LDB clock\n");
 182
 183         /* Configure CCM_CSCMR2 */
 184         clrsetbits_le32(&mxc_ccm->cscmr2,
 185                         (0x7 << 26) | BIT(10) | BIT(8),
 186                         (0x5 << 26) | BIT(10) | BIT(8));
 187
 188         /* Configure LDB_CTRL */
 189         writel(0x201, 0x53fa8008);
 190 }
 191
 192 static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
 193 {
 194         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 195
 196         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 197         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 198
 199         /*
 200          * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
 201          * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 202          */
 203         enable_lvds_clock(dev, 63);
 204 }
 205
 206 static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
 207 {
 208         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 209
 210         /*
 211          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 212          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 213          */
 214         enable_lvds_clock(dev, 233);
 215
 216         /* For ETM0700G0DH6 model, this may be enabled after the clock. */
 217         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 218 }
 219
 220 static const char *lvds_compat_string;
 221
 222 static int detect_lvds(struct display_info_t const *dev)
 223 {
 224         u8 touchid[23];
 225         u8 *touchptr = &touchid[0];
 226         int ret;
 227
 228         ret = i2c_set_bus_num(0);
 229         if (ret)
 230                 return 0;
 231
 232         /* Touchscreen is at address 0x38, ID register is 0xbb. */
 233         ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
 234         if (ret)
 235                 return 0;
 236
 237         /* EP0430 prefixes the response with 0xbb, skip it. */
 238         if (*touchptr == 0xbb)
 239                 touchptr++;
 240
 241         /* Skip the 'EP' prefix. */
 242         touchptr += 2;
 243
 244         ret = !memcmp(touchptr, &dev->mode.name[7], 4);
 245         if (ret)
 246                 lvds_compat_string = dev->mode.name;
 247
 248         return ret;
 249 }
 250
 251 void board_preboot_os(void)
 252 {
 253         /* Power off the LCD to prevent awful color flicker */
 254         gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
 255 }
 256
 257 int ft_board_setup(void *blob, bd_t *bd)
 258 {
 259         if (lvds_compat_string)
 260                 do_fixup_by_path_string(blob, "/panel", "compatible",
 261                                         lvds_compat_string);
 262
 263         return 0;
 264 }
 265
 266 struct display_info_t const displays[] = {
 267         {
 268                 .bus    = 0,
 269                 .addr   = 0,
 270                 .detect = detect_lvds,
 271                 .enable = enable_lvds_etm0430g0dh6,
 272                 .pixfmt = IPU_PIX_FMT_RGB666,
 273                 .mode   = {
 274                         .name           = "edt,etm0430g0dh6",
 275                         .refresh        = 60,
 276                         .xres           = 480,
 277                         .yres           = 272,
 278                         .pixclock       = 111111, /* picosecond (9 MHz) */
 279                         .left_margin    = 2,
 280                         .right_margin   = 2,
 281                         .upper_margin   = 2,
 282                         .lower_margin   = 2,
 283                         .hsync_len      = 41,
 284                         .vsync_len      = 10,
 285                         .sync           = 0x40000000,
 286                         .vmode          = FB_VMODE_NONINTERLACED
 287                 }
 288         }, {
 289                 .bus    = 0,
 290                 .addr   = 0,
 291                 .detect = detect_lvds,
 292                 .enable = enable_lvds_etm0700g0dh6,
 293                 .pixfmt = IPU_PIX_FMT_RGB666,
 294                 .mode   = {
 295                         .name           = "edt,etm0700g0dh6",
 296                         .refresh        = 60,
 297                         .xres           = 800,
 298                         .yres           = 480,
 299                         .pixclock       = 30048, /* picosecond (33.28 MHz) */
 300                         .left_margin    = 40,
 301                         .right_margin   = 88,
 302                         .upper_margin   = 10,
 303                         .lower_margin   = 33,
 304                         .hsync_len      = 128,
 305                         .vsync_len      = 2,
 306                         .sync           = FB_SYNC_EXT,
 307                         .vmode          = FB_VMODE_NONINTERLACED
 308                 }
 309         }
 310 };
 311
 312 size_t display_count = ARRAY_SIZE(displays);
 313
 314 #ifdef CONFIG_SPLASH_SCREEN
 315 static struct splash_location default_splash_locations[] = {
 316         {
 317                 .name           = "mmc_fs",
 318                 .storage        = SPLASH_STORAGE_MMC,
 319                 .flags          = SPLASH_STORAGE_FS,
 320                 .devpart        = "0:1",
 321         },
 322 };
 323
 324 int splash_screen_prepare(void)
 325 {
 326         return splash_source_load(default_splash_locations,
 327                                   ARRAY_SIZE(default_splash_locations));
 328 }
 329 #endif
 330
 331 int board_late_init(void)
 332 {
 333 #if defined(CONFIG_VIDEO_IPUV3)
 334         struct udevice *dev;
 335         int xpos, ypos, ret;
 336         char *s;
 337         void *dst;
 338         ulong addr, len;
 339
 340         splash_get_pos(&xpos, &ypos);
 341
 342         s = env_get("splashimage");
 343         if (!s)
 344                 return 0;
 345
 346         addr = simple_strtoul(s, NULL, 16);
 347         dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
 348         if (!dst)
 349                 return -ENOMEM;
 350
 351         ret = splash_screen_prepare();
 352         if (ret < 0)
 353                 return ret;
 354
 355         len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
 356         ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
 357                      (uchar *)addr, &len);
 358         if (ret) {
 359                 printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
 360                 free(dst);
 361                 return ret;
 362         }
 363
 364         ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
 365         if (ret)
 366                 return ret;
 367
 368         ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
 369         if (ret)
 370                 return ret;
 371 #endif
 372         return 0;
 373 }
 374
 375 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 376                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 377
 378 static void setup_iomux_i2c(void)
 379 {
 380         static const iomux_v3_cfg_t i2c_pads[] = {
 381                 /* I2C1 */
 382                 NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
 383                 NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
 384                 /* I2C2 */
 385                 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
 386                 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
 387         };
 388
 389         imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 390 }
 391
 392 static void setup_iomux_video(void)
 393 {
 394         static const iomux_v3_cfg_t lcd_pads[] = {
 395                 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 396                 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 397                 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 398                 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 399                 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 400         };
 401
 402         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 403 }
 404
 405 static void setup_iomux_nand(void)
 406 {
 407         static const iomux_v3_cfg_t nand_pads[] = {
 408                 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
 409                              PAD_CTL_DSE_HIGH),
 410                 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
 411                              PAD_CTL_DSE_HIGH),
 412                 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
 413                              PAD_CTL_DSE_HIGH),
 414                 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
 415                              PAD_CTL_DSE_HIGH),
 416                 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
 417                              PAD_CTL_PUS_100K_UP),
 418                 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
 419                              PAD_CTL_PUS_100K_UP),
 420                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
 421                              PAD_CTL_DSE_HIGH),
 422                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
 423                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 424                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
 425                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 426                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
 427                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 428                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
 429                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 430                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
 431                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 432                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
 433                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 434                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
 435                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 436                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
 437                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 438         };
 439
 440         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 441 }
 442
 443 static void m53_set_clock(void)
 444 {
 445         int ret;
 446         const u32 ref_clk = MXC_HCLK;
 447         const u32 dramclk = 400;
 448         u32 cpuclk;
 449
 450         gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
 451
 452         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
 453                                             PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
 454         gpio_direction_input(IMX_GPIO_NR(4, 0));
 455
 456         /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
 457         cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
 458
 459         ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
 460         if (ret)
 461                 printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
 462
 463         ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
 464         if (ret) {
 465                 printf("CPU:   Switch peripheral clock to %dMHz failed\n",
 466                        dramclk);
 467         }
 468
 469         ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
 470         if (ret)
 471                 printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
 472 }
 473
 474 static void m53_set_nand(void)
 475 {
 476         u32 i;
 477
 478         /* NAND flash is muxed on ATA pins */
 479         setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
 480
 481         /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
 482         for (i = 0x4; i < 0x94; i += 0x18) {
 483                 clrbits_le32(WEIM_BASE_ADDR + i,
 484                              WEIM_GCR2_MUX16_BYP_GRANT_MASK);
 485         }
 486
 487         mxc_set_clock(0, 33, MXC_NFC_CLK);
 488         enable_nfc_clk(1);
 489 }
 490
 491 int board_early_init_f(void)
 492 {
 493         setup_iomux_uart();
 494         setup_iomux_fec();
 495         setup_iomux_i2c();
 496         setup_iomux_nand();
 497         setup_iomux_video();
 498
 499         m53_set_clock();
 500
 501         mxc_set_sata_internal_clock();
 502
 503         /* NAND clock @ 33MHz */
 504         m53_set_nand();
 505
 506         return 0;
 507 }
 508
 509 int board_init(void)
 510 {
 511         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 512
 513         return 0;
 514 }
 515
 516 int checkboard(void)
 517 {
 518         puts("Board: Menlosystems M53Menlo\n");
 519
 520         return 0;
 521 }
 522
 523 /*
 524  * NAND SPL
 525  */
 526 #ifdef CONFIG_SPL_BUILD
 527 void spl_board_init(void)
 528 {
 529         setup_iomux_nand();
 530         m53_set_clock();
 531         m53_set_nand();
 532 }
 533
 534 u32 spl_boot_device(void)
 535 {
 536         return BOOT_DEVICE_NAND;
 537 }
 538 #endif