board/menlo/m53menlo/m53menlo.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Menlosystems M53Menlo board
   4  *
   5  * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
   6  * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/iomux-mx53.h>
  17 #include <asm/mach-imx/mx5_video.h>
  18 #include <asm/mach-imx/video.h>
  19 #include <asm/gpio.h>
  20 #include <asm/spl.h>
  21 #include <fdt_support.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <gzip.h>
  24 #include <i2c.h>
  25 #include <ipu_pixfmt.h>
  26 #include <linux/errno.h>
  27 #include <linux/fb.h>
  28 #include <mmc.h>
  29 #include <netdev.h>
  30 #include <spl.h>
  31 #include <splash.h>
  32 #include <usb/ehci-ci.h>
  33 #include <video_console.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 static u32 mx53_dram_size[2];
  38
  39 ulong board_get_usable_ram_top(ulong total_size)
  40 {
  41         /*
  42          * WARNING: We must override get_effective_memsize() function here
  43          * to report only the size of the first DRAM bank. This is to make
  44          * U-Boot relocator place U-Boot into valid memory, that is, at the
  45          * end of the first DRAM bank. If we did not override this function
  46          * like so, U-Boot would be placed at the address of the first DRAM
  47          * bank + total DRAM size - sizeof(uboot), which in the setup where
  48          * each DRAM bank contains 512MiB of DRAM would result in placing
  49          * U-Boot into invalid memory area close to the end of the first
  50          * DRAM bank.
  51          */
  52         return PHYS_SDRAM_2 + mx53_dram_size[1];
  53 }
  54
  55 int dram_init(void)
  56 {
  57         mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
  58         mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
  59
  60         gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
  61
  62         return 0;
  63 }
  64
  65 int dram_init_banksize(void)
  66 {
  67         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  68         gd->bd->bi_dram[0].size = mx53_dram_size[0];
  69
  70         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  71         gd->bd->bi_dram[1].size = mx53_dram_size[1];
  72
  73         return 0;
  74 }
  75
  76 static void setup_iomux_uart(void)
  77 {
  78         static const iomux_v3_cfg_t uart_pads[] = {
  79                 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  80                 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  81         };
  82
  83         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  84 }
  85
  86 static void setup_iomux_fec(void)
  87 {
  88         static const iomux_v3_cfg_t fec_pads[] = {
  89                 /* MDIO pads */
  90                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  91                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  92                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  93
  94                 /* FEC 0 pads */
  95                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  96                              PAD_CTL_HYS | PAD_CTL_PKE),
  97                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  98                              PAD_CTL_HYS | PAD_CTL_PKE),
  99                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 100                              PAD_CTL_HYS | PAD_CTL_PKE),
 101                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
 102                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 103                              PAD_CTL_HYS | PAD_CTL_PKE),
 104                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 105                              PAD_CTL_HYS | PAD_CTL_PKE),
 106                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 107                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 108
 109                 /* FEC 1 pads */
 110                 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
 111                              PAD_CTL_HYS | PAD_CTL_PKE),
 112                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
 113                              PAD_CTL_HYS | PAD_CTL_PKE),
 114                 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
 115                              PAD_CTL_HYS | PAD_CTL_PKE),
 116                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
 117                              PAD_CTL_HYS | PAD_CTL_PKE),
 118                 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
 119                              PAD_CTL_HYS | PAD_CTL_PKE),
 120                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
 121                 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
 122                              PAD_CTL_HYS | PAD_CTL_PKE),
 123                 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
 124         };
 125
 126         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 127 }
 128
 129 #ifdef CONFIG_FSL_ESDHC_IMX
 130 struct fsl_esdhc_cfg esdhc_cfg = {
 131         MMC_SDHC1_BASE_ADDR,
 132 };
 133
 134 int board_mmc_getcd(struct mmc *mmc)
 135 {
 136         imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
 137         gpio_direction_input(IMX_GPIO_NR(1, 1));
 138
 139         return !gpio_get_value(IMX_GPIO_NR(1, 1));
 140 }
 141
 142 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 143                                  PAD_CTL_PUS_100K_UP)
 144 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 145                                  PAD_CTL_DSE_HIGH)
 146
 147 int board_mmc_init(bd_t *bis)
 148 {
 149         static const iomux_v3_cfg_t sd1_pads[] = {
 150                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 151                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 152                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 153                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 154                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 155                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 156         };
 157
 158         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 159
 160         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 161
 162         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 163 }
 164 #endif
 165
 166 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
 167 {
 168         static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 169         int ret;
 170
 171         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 172         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 173
 174         /*
 175          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 176          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 177          */
 178         ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
 179         if (ret)
 180                 puts("IPU:   Failed to configure LDB clock\n");
 181
 182         /* Configure CCM_CSCMR2 */
 183         clrsetbits_le32(&mxc_ccm->cscmr2,
 184                         (0x7 << 26) | BIT(10) | BIT(8),
 185                         (0x5 << 26) | BIT(10) | BIT(8));
 186
 187         /* Configure LDB_CTRL */
 188         writel(0x201, 0x53fa8008);
 189 }
 190
 191 static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
 192 {
 193         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 194
 195         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 196         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 197
 198         /*
 199          * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
 200          * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 201          */
 202         enable_lvds_clock(dev, 63);
 203 }
 204
 205 static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
 206 {
 207         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 208
 209         /*
 210          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 211          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 212          */
 213         enable_lvds_clock(dev, 233);
 214
 215         /* For ETM0700G0DH6 model, this may be enabled after the clock. */
 216         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 217 }
 218
 219 static const char *lvds_compat_string;
 220
 221 static int detect_lvds(struct display_info_t const *dev)
 222 {
 223         u8 touchid[23];
 224         u8 *touchptr = &touchid[0];
 225         int ret;
 226
 227         ret = i2c_set_bus_num(0);
 228         if (ret)
 229                 return 0;
 230
 231         /* Touchscreen is at address 0x38, ID register is 0xbb. */
 232         ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
 233         if (ret)
 234                 return 0;
 235
 236         /* EP0430 prefixes the response with 0xbb, skip it. */
 237         if (*touchptr == 0xbb)
 238                 touchptr++;
 239
 240         /* Skip the 'EP' prefix. */
 241         touchptr += 2;
 242
 243         ret = !memcmp(touchptr, &dev->mode.name[7], 4);
 244         if (ret)
 245                 lvds_compat_string = dev->mode.name;
 246
 247         return ret;
 248 }
 249
 250 void board_preboot_os(void)
 251 {
 252         /* Power off the LCD to prevent awful color flicker */
 253         gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
 254 }
 255
 256 int ft_board_setup(void *blob, bd_t *bd)
 257 {
 258         if (lvds_compat_string)
 259                 do_fixup_by_path_string(blob, "/panel", "compatible",
 260                                         lvds_compat_string);
 261
 262         return 0;
 263 }
 264
 265 struct display_info_t const displays[] = {
 266         {
 267                 .bus    = 0,
 268                 .addr   = 0,
 269                 .detect = detect_lvds,
 270                 .enable = enable_lvds_etm0430g0dh6,
 271                 .pixfmt = IPU_PIX_FMT_RGB666,
 272                 .mode   = {
 273                         .name           = "edt,etm0430g0dh6",
 274                         .refresh        = 60,
 275                         .xres           = 480,
 276                         .yres           = 272,
 277                         .pixclock       = 111111, /* picosecond (9 MHz) */
 278                         .left_margin    = 2,
 279                         .right_margin   = 2,
 280                         .upper_margin   = 2,
 281                         .lower_margin   = 2,
 282                         .hsync_len      = 41,
 283                         .vsync_len      = 10,
 284                         .sync           = 0x40000000,
 285                         .vmode          = FB_VMODE_NONINTERLACED
 286                 }
 287         }, {
 288                 .bus    = 0,
 289                 .addr   = 0,
 290                 .detect = detect_lvds,
 291                 .enable = enable_lvds_etm0700g0dh6,
 292                 .pixfmt = IPU_PIX_FMT_RGB666,
 293                 .mode   = {
 294                         .name           = "edt,etm0700g0dh6",
 295                         .refresh        = 60,
 296                         .xres           = 800,
 297                         .yres           = 480,
 298                         .pixclock       = 30048, /* picosecond (33.28 MHz) */
 299                         .left_margin    = 40,
 300                         .right_margin   = 88,
 301                         .upper_margin   = 10,
 302                         .lower_margin   = 33,
 303                         .hsync_len      = 128,
 304                         .vsync_len      = 2,
 305                         .sync           = FB_SYNC_EXT,
 306                         .vmode          = FB_VMODE_NONINTERLACED
 307                 }
 308         }
 309 };
 310
 311 size_t display_count = ARRAY_SIZE(displays);
 312
 313 #ifdef CONFIG_SPLASH_SCREEN
 314 static struct splash_location default_splash_locations[] = {
 315         {
 316                 .name           = "mmc_fs",
 317                 .storage        = SPLASH_STORAGE_MMC,
 318                 .flags          = SPLASH_STORAGE_FS,
 319                 .devpart        = "0:1",
 320         },
 321 };
 322
 323 int splash_screen_prepare(void)
 324 {
 325         return splash_source_load(default_splash_locations,
 326                                   ARRAY_SIZE(default_splash_locations));
 327 }
 328 #endif
 329
 330 int board_late_init(void)
 331 {
 332 #if defined(CONFIG_VIDEO_IPUV3)
 333         struct udevice *dev;
 334         int xpos, ypos, ret;
 335         char *s;
 336         void *dst;
 337         ulong addr, len;
 338
 339         splash_get_pos(&xpos, &ypos);
 340
 341         s = env_get("splashimage");
 342         if (!s)
 343                 return 0;
 344
 345         addr = simple_strtoul(s, NULL, 16);
 346         dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
 347         if (!dst)
 348                 return -ENOMEM;
 349
 350         ret = splash_screen_prepare();
 351         if (ret < 0)
 352                 return ret;
 353
 354         len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
 355         ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
 356                      (uchar *)addr, &len);
 357         if (ret) {
 358                 printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
 359                 free(dst);
 360                 return ret;
 361         }
 362
 363         ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
 364         if (ret)
 365                 return ret;
 366
 367         ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
 368         if (ret)
 369                 return ret;
 370 #endif
 371         return 0;
 372 }
 373
 374 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 375                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 376
 377 static void setup_iomux_i2c(void)
 378 {
 379         static const iomux_v3_cfg_t i2c_pads[] = {
 380                 /* I2C1 */
 381                 NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
 382                 NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
 383                 /* I2C2 */
 384                 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
 385                 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
 386         };
 387
 388         imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 389 }
 390
 391 static void setup_iomux_video(void)
 392 {
 393         static const iomux_v3_cfg_t lcd_pads[] = {
 394                 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 395                 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 396                 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 397                 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 398                 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 399         };
 400
 401         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 402 }
 403
 404 static void setup_iomux_nand(void)
 405 {
 406         static const iomux_v3_cfg_t nand_pads[] = {
 407                 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
 408                              PAD_CTL_DSE_HIGH),
 409                 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
 410                              PAD_CTL_DSE_HIGH),
 411                 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
 412                              PAD_CTL_DSE_HIGH),
 413                 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
 414                              PAD_CTL_DSE_HIGH),
 415                 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
 416                              PAD_CTL_PUS_100K_UP),
 417                 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
 418                              PAD_CTL_PUS_100K_UP),
 419                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
 420                              PAD_CTL_DSE_HIGH),
 421                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
 422                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 423                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
 424                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 425                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
 426                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 427                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
 428                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 429                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
 430                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 431                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
 432                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 433                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
 434                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 435                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
 436                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 437         };
 438
 439         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 440 }
 441
 442 static void m53_set_clock(void)
 443 {
 444         int ret;
 445         const u32 ref_clk = MXC_HCLK;
 446         const u32 dramclk = 400;
 447         u32 cpuclk;
 448
 449         gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
 450
 451         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
 452                                             PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
 453         gpio_direction_input(IMX_GPIO_NR(4, 0));
 454
 455         /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
 456         cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
 457
 458         ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
 459         if (ret)
 460                 printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
 461
 462         ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
 463         if (ret) {
 464                 printf("CPU:   Switch peripheral clock to %dMHz failed\n",
 465                        dramclk);
 466         }
 467
 468         ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
 469         if (ret)
 470                 printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
 471 }
 472
 473 static void m53_set_nand(void)
 474 {
 475         u32 i;
 476
 477         /* NAND flash is muxed on ATA pins */
 478         setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
 479
 480         /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
 481         for (i = 0x4; i < 0x94; i += 0x18) {
 482                 clrbits_le32(WEIM_BASE_ADDR + i,
 483                              WEIM_GCR2_MUX16_BYP_GRANT_MASK);
 484         }
 485
 486         mxc_set_clock(0, 33, MXC_NFC_CLK);
 487         enable_nfc_clk(1);
 488 }
 489
 490 int board_early_init_f(void)
 491 {
 492         setup_iomux_uart();
 493         setup_iomux_fec();
 494         setup_iomux_i2c();
 495         setup_iomux_nand();
 496         setup_iomux_video();
 497
 498         m53_set_clock();
 499
 500         mxc_set_sata_internal_clock();
 501
 502         /* NAND clock @ 33MHz */
 503         m53_set_nand();
 504
 505         return 0;
 506 }
 507
 508 int board_init(void)
 509 {
 510         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 511
 512         return 0;
 513 }
 514
 515 int checkboard(void)
 516 {
 517         puts("Board: Menlosystems M53Menlo\n");
 518
 519         return 0;
 520 }
 521
 522 /*
 523  * NAND SPL
 524  */
 525 #ifdef CONFIG_SPL_BUILD
 526 void spl_board_init(void)
 527 {
 528         setup_iomux_nand();
 529         m53_set_clock();
 530         m53_set_nand();
 531 }
 532
 533 u32 spl_boot_device(void)
 534 {
 535         return BOOT_DEVICE_NAND;
 536 }
 537 #endif