3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
6 * Board specific routines for the MBX
9 * - interface to VPD data (mac address, clock speeds)
11 * - serial io initialisation
12 * - ethernet io initialisation
14 * -----------------------------------------------------------------
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42 /* ------------------------------------------------------------------------- */
44 static const uint sdram_table_40[] = {
45 /* DRAM - single read. (offset 0 in upm RAM)
47 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00,
48 0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
50 /* DRAM - burst read. (offset 8 in upm RAM)
52 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08,
53 0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08,
54 0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005,
55 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
57 /* DRAM - single write. (offset 18 in upm RAM)
59 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804,
60 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
62 /* DRAM - burst write. (offset 20 in upm RAM)
64 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
65 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
66 0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005,
67 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
69 /* refresh (offset 30 in upm RAM)
71 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
72 0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
73 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
75 /* exception. (offset 3c in upm RAM)
77 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
80 static const uint sdram_table_50[] = {
81 /* DRAM - single read. (offset 0 in upm RAM)
83 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04,
84 0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005,
86 /* DRAM - burst read. (offset 8 in upm RAM)
88 0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04,
89 /* 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04, */
90 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08,
91 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04,
92 /* 0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005, */
93 0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005,
95 /* DRAM - single write. (offset 18 in upm RAM)
97 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804,
98 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
100 /* DRAM - burst write. (offset 20 in upm RAM)
102 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
103 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
104 0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005,
105 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
107 /* refresh (offset 30 in upm RAM)
109 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
110 0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005,
111 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
113 /* exception. (offset 3c in upm RAM)
115 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
118 /* ------------------------------------------------------------------------- */
120 #ifdef CONFIG_SYS_USE_OSCCLK
121 static unsigned int get_reffreq(void);
123 static unsigned int board_get_cpufreq(void);
127 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
128 volatile memctl8xx_t *memctl = &immr->im_memctl;
129 ulong speed, plprcr, sccr;
130 ulong br0_32 = memctl->memc_br0 & 0x400;
132 /* real-time clock status and control register */
133 immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
134 immr->im_sit.sit_rtcsc = 0x00C3;
136 /* SIEL and SIMASK Registers (see MBX PRG 2-3) */
137 immr->im_siu_conf.sc_simask = 0x00000000;
138 immr->im_siu_conf.sc_siel = 0xAAAA0000;
139 immr->im_siu_conf.sc_tesr = 0xFFFFFFFF;
142 * Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus:
143 * 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h)
144 * 2. RAM Specs (see dimm.h)
145 * 2. DIMM Specs (see dimm.h)
149 /* system clock and reset control register */
150 immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
151 sccr = immr->im_clkrst.car_sccr;
153 sccr |= CONFIG_SYS_SCCR;
154 immr->im_clkrst.car_sccr = sccr;
156 speed = board_get_cpufreq ();
158 #if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0)
159 plprcr = CONFIG_SYS_PLPRCR;
161 plprcr = immr->im_clkrst.car_plprcr;
162 plprcr &= PLPRCR_MF_MSK; /* isolate MF field */
163 plprcr |= CONFIG_SYS_PLPRCR; /* reset control bits */
166 #ifdef CONFIG_SYS_USE_OSCCLK /* See doc/README.MBX ! */
167 plprcr |= ((speed + get_reffreq() / 2) / refclock - 1) << 20;
170 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
171 immr->im_clkrst.car_plprcr = plprcr;
174 * preliminary setup of memory controller:
175 * - map Flash, otherwise configuration/status
176 * registers won't be accessible when read
178 * - map NVRAM and configuation/status registers.
179 * - map pci registers.
180 * - DON'T map ram yet, this is done in initdram().
182 switch (speed / 1000000) {
184 memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
185 memctl->memc_or0 = 0xFF800930;
186 memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x920;
187 memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401;
190 memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
191 memctl->memc_or0 = 0xFF800940;
192 memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x930;
193 memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401;
199 #ifdef CONFIG_USE_PCI
200 memctl->memc_or5 = CONFIG_SYS_PCIMEM_OR;
201 memctl->memc_br5 = CONFIG_SYS_PCIMEM_BASE | 0x001;
202 memctl->memc_or6 = CONFIG_SYS_PCIBRIDGE_OR;
203 memctl->memc_br6 = CONFIG_SYS_PCIBRIDGE_BASE | 0x001;
206 * FIXME: I do not understand why I have to call this to
207 * initialise the control register here before booting from
208 * the PCMCIA card but if I do not the Linux kernel falls
209 * over in a big heap. If you can answer this question I
210 * would like to know about it.
215 void board_serial_init (void)
217 MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS);
220 void board_ether_init (void)
222 MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN);
223 MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS;
226 static unsigned int board_get_cpufreq (void)
228 #ifndef CONFIG_8xx_GCLK_FREQ
229 vpd_packet_t *packet;
232 packet = vpd_find_packet (VPD_PID_ICS);
233 p = (ulong *)packet->data;
236 return((unsigned int)CONFIG_8xx_GCLK_FREQ );
237 #endif /* CONFIG_8xx_GCLK_FREQ */
240 #ifdef CONFIG_SYS_USE_OSCCLK
241 static unsigned int get_reffreq (void)
243 vpd_packet_t *packet;
246 packet = vpd_find_packet (VPD_PID_RCS);
247 p = (ulong *)packet->data;
252 static void board_get_enetaddr(uchar *addr)
255 vpd_packet_t *packet;
257 packet = vpd_find_packet (VPD_PID_EA);
258 for (i = 0; i < 6; i++)
259 addr[i] = packet->data[i];
262 int misc_init_r(void)
266 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
267 board_get_enetaddr(enetaddr);
268 eth_setenv_enetaddr("ethaddr", enetaddr);
275 * Check Board Identity:
278 int checkboard (void)
280 vpd_packet_t *packet;
282 const char *const fmt =
283 "\n *** Warning: Low Battery Status - %s Battery ***";
287 packet = vpd_find_packet (VPD_PID_PID);
288 for (i = 0; i < packet->size; i++) {
289 serial_putc (packet->data[i]);
291 packet = vpd_find_packet (VPD_PID_MT);
292 for (i = 0; i < packet->size; i++) {
293 serial_putc (packet->data[i]);
296 packet = vpd_find_packet (VPD_PID_FAN);
297 for (i = 0; i < packet->size; i++) {
298 serial_putc (packet->data[i]);
302 if (!(MBX_CSR2 & SR2_BATGD))
303 printf (fmt, "On-Board");
304 if (!(MBX_CSR2 & SR2_NVBATGD))
305 printf (fmt, "NVRAM");
312 /* ------------------------------------------------------------------------- */
314 static ulong get_ramsize (dimm_t * dimm)
318 if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3
320 size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks *
321 ((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8);
327 phys_size_t initdram (int board_type)
329 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
330 volatile memctl8xx_t *memctl = &immap->im_memctl;
331 unsigned long ram_sz = 0;
332 unsigned long dimm_sz = 0;
333 dimm_t vpd_dimm, vpd_dram;
334 unsigned int speed = board_get_cpufreq () / 1000000;
336 if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) {
337 dimm_sz = get_ramsize (&vpd_dimm);
339 if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) {
340 ram_sz = get_ramsize (&vpd_dram);
344 * Only initialize memory controller when running from FLASH.
345 * When running from RAM, don't touch it.
347 if ((ulong) initdram & 0xff000000) {
349 ulong br0_32 = memctl->memc_br0 & 0x400;
353 upmconfig (UPMA, (uint *) sdram_table_40,
354 sizeof (sdram_table_40) / sizeof (uint));
355 memctl->memc_mptpr = 0x0200;
356 memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000;
357 memctl->memc_or7 = 0xff800930;
358 memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
361 upmconfig (UPMA, (uint *) sdram_table_50,
362 sizeof (sdram_table_50) / sizeof (uint));
363 memctl->memc_mptpr = 0x0200;
364 memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100;
365 memctl->memc_or7 = 0xff800940;
366 memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
373 /* now map ram and dimm, largest one first */
374 dimm_bank = dimm_sz / 2;
376 memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
377 memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81;
378 memctl->memc_br2 = 0;
379 memctl->memc_br3 = 0;
380 } else if (ram_sz > dimm_bank) {
381 memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
382 memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81;
383 memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
384 memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE + ram_sz) | 0x81;
385 memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
386 memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + ram_sz + dimm_bank) \
389 memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
390 memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x81;
391 memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
392 memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + dimm_bank) | 0x81;
393 memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
394 memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE + dimm_sz) | 0x81;
398 return ram_sz + dimm_sz;