3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2005-2007
9 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <environment.h>
37 #include <fdt_support.h>
42 #include "../common/mv_common.h"
44 #define SDRAM_MODE 0x00CD0000
45 #define SDRAM_CONTROL 0x504F0000
46 #define SDRAM_CONFIG1 0xD2322800
47 #define SDRAM_CONFIG2 0x8AD70000
49 DECLARE_GLOBAL_DATA_PTR;
51 static void sdram_start (int hi_addr)
53 long hi_bit = hi_addr ? 0x01000000 : 0;
55 /* unlock mode register */
56 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
58 /* precharge all banks */
59 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
61 /* precharge all banks */
62 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
65 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
67 /* set mode register */
68 out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
70 /* normal operation */
71 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
74 phys_addr_t initdram (int board_type)
80 /* setup SDRAM chip selects */
81 out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
83 /* setup config registers */
84 out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
85 out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
87 /* find RAM size using SDRAM CS0 only */
89 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
91 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
98 if (dramsize < (1 << 20))
102 out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
103 __builtin_ffs(dramsize >> 20) - 1);
105 out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
110 void mvbc_init_gpio(void)
112 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
114 printf("Ports : 0x%08x\n", gpio->port_config);
115 printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
117 out_be32(&gpio->simple_ddr, SIMPLE_DDR);
118 out_be32(&gpio->simple_dvo, SIMPLE_DVO);
119 out_be32(&gpio->simple_ode, SIMPLE_ODE);
120 out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
122 out_8(&gpio->sint_ode, SINT_ODE);
123 out_8(&gpio->sint_ddr, SINT_DDR);
124 out_8(&gpio->sint_dvo, SINT_DVO);
125 out_8(&gpio->sint_inten, SINT_INTEN);
126 out_be16(&gpio->sint_itype, SINT_ITYPE);
127 out_8(&gpio->sint_gpioe, SINT_GPIOEN);
129 out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
130 out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
131 out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
132 out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
134 printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
135 printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
138 int misc_init_r(void)
140 char *s = getenv("reset_env");
143 if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
146 if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
149 if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
152 printf(" === FACTORY RESET ===\n");
153 mv_reset_environment();
162 printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
167 void flash_preinit(void)
170 * Now, when we are in RAM, enable flash write
171 * access for detection process.
172 * Note that CS_BOOT cannot be cleared when
173 * executing in flash.
175 clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
178 void flash_afterinit(ulong size)
180 out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
182 out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
184 out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
186 out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
190 void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
192 unsigned char line = 0xff;
193 char *s = getenv("pci_latency");
198 val = simple_strtoul(s, NULL, 16);
200 if (PCI_BUS(dev) == 0) {
201 switch (PCI_DEV (dev)) {
204 pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
205 printf("found FPGA - enable arbitration\n");
206 writel(0x03, (u32*)(base + 0x80c0));
207 writel(0xf0, (u32*)(base + 0x8080));
209 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
214 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
219 printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
222 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
226 struct pci_controller hose = {
227 fixup_irq:pci_mvbc_fixup_irq
230 extern void pci_mpc5xxx_init(struct pci_controller *);
232 void pci_init_board(void)
236 pci_mpc5xxx_init(&hose);
239 void show_boot_progress(int val)
241 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
244 case 0: /* FPGA ok */
245 setbits_be32(&gpio->simple_dvo, LED_G0);
248 setbits_be32(&gpio->simple_dvo, LED_G1);
251 setbits_be32(&gpio->simple_dvo, LED_Y);
254 setbits_be32(&gpio->simple_dvo, LED_R);
262 void ft_board_setup(void *blob, bd_t *bd)
264 ft_cpu_setup(blob, bd);
267 int board_eth_init(bd_t *bis)
269 cpu_eth_init(bis); /* Built in FEC comes first */
270 return pci_eth_init(bis);