3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2005-2007
9 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <environment.h>
37 #include <fdt_support.h>
42 #define SDRAM_MODE 0x00CD0000
43 #define SDRAM_CONTROL 0x504F0000
44 #define SDRAM_CONFIG1 0xD2322800
45 #define SDRAM_CONFIG2 0x8AD70000
47 DECLARE_GLOBAL_DATA_PTR;
49 static void sdram_start (int hi_addr)
51 long hi_bit = hi_addr ? 0x01000000 : 0;
53 /* unlock mode register */
54 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
56 /* precharge all banks */
57 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
59 /* precharge all banks */
60 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
63 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
65 /* set mode register */
66 out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
68 /* normal operation */
69 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
72 phys_addr_t initdram (int board_type)
78 /* setup SDRAM chip selects */
79 out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
81 /* setup config registers */
82 out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
83 out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
85 /* find RAM size using SDRAM CS0 only */
87 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
89 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
96 if (dramsize < (1 << 20))
100 out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
101 __builtin_ffs(dramsize >> 20) - 1);
103 out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
108 void mvbc_init_gpio(void)
110 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
112 printf("Ports : 0x%08x\n", gpio->port_config);
113 printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
115 out_be32(&gpio->simple_ddr, SIMPLE_DDR);
116 out_be32(&gpio->simple_dvo, SIMPLE_DVO);
117 out_be32(&gpio->simple_ode, SIMPLE_ODE);
118 out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
120 out_be32((u32*)&gpio->sint_ode, SINT_ODE);
121 out_be32((u32*)&gpio->sint_ddr, SINT_DDR);
122 out_be32((u32*)&gpio->sint_dvo, SINT_DVO);
123 out_be32((u32*)&gpio->sint_inten, SINT_INTEN);
124 out_be32((u32*)&gpio->sint_itype, SINT_ITYPE);
125 out_be32((u32*)&gpio->sint_gpioe, SINT_GPIOEN);
127 out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
128 out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
129 out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
130 out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
132 printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
133 printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
136 void reset_environment(void)
140 printf("\n*** RESET ENVIRONMENT ***\n");
141 memset(sernr, 0, sizeof(sernr));
142 s = getenv("serial#");
144 printf("found serial# : %s\n", s);
145 strncpy(sernr, s, 64);
150 setenv("serial#", sernr);
153 int misc_init_r(void)
155 char *s = getenv("reset_env");
158 if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
161 if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
164 if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
167 printf(" === FACTORY RESET ===\n");
177 printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
182 void flash_preinit(void)
185 * Now, when we are in RAM, enable flash write
186 * access for detection process.
187 * Note that CS_BOOT cannot be cleared when
188 * executing in flash.
190 clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
193 void flash_afterinit(ulong size)
195 out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CFG_BOOTCS_START |
197 out_be32((u32*)MPC5XXX_CS0_START, START_REG(CFG_BOOTCS_START |
199 out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CFG_BOOTCS_START | size,
201 out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CFG_BOOTCS_START | size,
205 void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
207 unsigned char line = 0xff;
210 if (PCI_BUS(dev) == 0) {
211 switch (PCI_DEV (dev)) {
214 pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
215 printf("found FPA - enable arbitration\n");
216 writel(0x03, (u32*)(base + 0x80c0));
217 writel(0xf0, (u32*)(base + 0x8080));
225 printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
228 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
232 struct pci_controller hose = {
233 fixup_irq:pci_mvbc_fixup_irq
236 int mvbc_p_load_fpga(void)
238 size_t data_size = 0;
239 void *fpga_data = NULL;
240 char *datastr = getenv("fpgadata");
241 char *sizestr = getenv("fpgadatasize");
244 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
246 data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
248 return fpga_load(0, fpga_data, data_size);
251 extern void pci_mpc5xxx_init(struct pci_controller *);
253 void pci_init_board(void)
259 s = getenv("skip_fpga");
261 printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
265 printf("loading FPGA ... ");
269 pci_mpc5xxx_init(&hose);
272 u8 *dhcp_vendorex_prep(u8 *e)
276 /* DHCP vendor-class-identifier = 60 */
277 if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
283 /* DHCP_CLIENT_IDENTIFIER = 61 */
284 if ((ptr = getenv("dhcp_client_id"))) {
294 u8 *dhcp_vendorex_proc (u8 *popt)
299 void show_boot_progress(int val)
301 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
304 case 0: /* FPGA ok */
305 setbits_be32(&gpio->simple_dvo, 0x80);
308 setbits_be32(&gpio->simple_dvo, 0x40);
311 setbits_be32(&gpio->simple_dvo, 0x20);
314 setbits_be32(&gpio->simple_dvo, 0x10);
322 void ft_board_setup(void *blob, bd_t *bd)
324 ft_cpu_setup(blob, bd);
325 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);