3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/processor.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
30 ulong flash_get_size (ulong base, int banknum);
32 int board_early_init_f(void)
34 u32 sdr0_pfc1, sdr0_pfc2;
37 /* PLB Write pipelining disabled. Denali Core workaround */
38 mtdcr(plb0_acr, 0xDE000000);
39 mtdcr(plb1_acr, 0xDE000000);
41 /*--------------------------------------------------------------------
42 * Setup the interrupt controller polarities, triggers, etc.
43 *-------------------------------------------------------------------*/
44 mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
45 mtdcr(uic0er, 0x00000000); /* disable all */
46 mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */
47 mtdcr(uic0pr, 0xfffff7ff); /* Adjustment of the polarity */
48 mtdcr(uic0tr, 0x00000810); /* per ref-board manual */
49 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
50 mtdcr(uic0sr, 0xffffffff); /* clear all */
52 mtdcr(uic1sr, 0xffffffff); /* clear all */
53 mtdcr(uic1er, 0x00000000); /* disable all */
54 mtdcr(uic1cr, 0x00000000); /* all non-critical */
55 mtdcr(uic1pr, 0xFFFFC7AD); /* Adjustment of the polarity */
56 mtdcr(uic1tr, 0x0600384A); /* per ref-board manual */
57 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
58 mtdcr(uic1sr, 0xffffffff); /* clear all */
60 mtdcr(uic2sr, 0xffffffff); /* clear all */
61 mtdcr(uic2er, 0x00000000); /* disable all */
62 mtdcr(uic2cr, 0x00000000); /* all non-critical */
63 mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */
64 mtdcr(uic2tr, 0xDFC00000); /* per ref-board manual */
65 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
66 mtdcr(uic2sr, 0xffffffff); /* clear all. Why this??? */
68 /* Trace Pins are disabled. SDR0_PFC0 Register */
69 mtsdr(SDR0_PFC0, 0x0);
71 /* select Ethernet pins */
72 mfsdr(SDR0_PFC1, sdr0_pfc1);
74 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
75 SDR0_PFC1_SELECT_CONFIG_6;
76 mfsdr(SDR0_PFC2, sdr0_pfc2);
77 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
78 SDR0_PFC2_SELECT_CONFIG_6;
80 /* enable SPI (SCP) */
81 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
83 mtsdr(SDR0_PFC2, sdr0_pfc2);
84 mtsdr(SDR0_PFC1, sdr0_pfc1);
86 mtsdr(SDR0_PFC4, 0x80000000);
88 /* PCI arbiter disabled */
89 /* PCI Host Configuration disbaled */
92 mtsdr(sdr_pci0, 0x00000000 | reg);
94 gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
99 /*---------------------------------------------------------------------------+
101 +---------------------------------------------------------------------------*/
102 int misc_init_r(void)
107 unsigned long usb2d0cr = 0;
108 unsigned long usb2phy0cr, usb2h0cr = 0;
109 unsigned long sdr0_pfc1;
115 /* Re-do sizing to get full correct info */
117 /* adjust flash start and offset */
118 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
119 gd->bd->bi_flashoffset = 0;
122 switch (gd->bd->bi_flashsize) {
148 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
152 * Re-check to get correct base address
154 flash_get_size(gd->bd->bi_flashstart, 0);
156 /* Monitor protection ON by default */
157 (void)flash_protect(FLAG_PROTECT_SET,
162 /* Env protection ON by default */
163 (void)flash_protect(FLAG_PROTECT_SET,
165 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
172 mfsdr(SDR0_PFC1, sdr0_pfc1);
173 mfsdr(SDR0_USB0, usb2d0cr);
174 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
175 mfsdr(SDR0_USB2H0CR, usb2h0cr);
177 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
178 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
179 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
180 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
181 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
182 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
183 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
184 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
185 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
186 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
188 /* An 8-bit/60MHz interface is the only possible alternative
189 when connecting the Device to the PHY */
190 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
191 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
193 mtsdr(SDR0_PFC1, sdr0_pfc1);
194 mtsdr(SDR0_USB0, usb2d0cr);
195 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
196 mtsdr(SDR0_USB2H0CR, usb2h0cr);
202 mtsdr(SDR0_SRST1, 0x00000000);
204 mtsdr(SDR0_SRST0, 0x00000000);
206 printf("USB: Host(int phy) Device(ext phy)\n");
209 * Clear PLB4A0_ACR[WRP]
210 * This fix will make the MAL burst disabling patch for the Linux
211 * EMAC driver obsolete.
213 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
214 mtdcr(plb4_acr, reg);
217 * Reset Lime controller
219 gpio_write_bit(CFG_GPIO_LIME_S, 1);
221 gpio_write_bit(CFG_GPIO_LIME_RST, 1);
226 gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
227 gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
229 gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
230 gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
235 gpio_write_bit(CFG_GPIO_HUB_RST, 0);
237 gpio_write_bit(CFG_GPIO_HUB_RST, 1);
244 char *s = getenv("serial#");
246 printf("Board: lwmon5");
257 #if defined(CFG_DRAM_TEST)
260 unsigned long *mem = (unsigned long *)0;
261 const unsigned long kend = (1024 / sizeof(unsigned long));
266 for (k = 0; k < CFG_MBYTES_SDRAM;
267 ++k, mem += (1024 / sizeof(unsigned long))) {
268 if ((k & 1023) == 0) {
269 printf("%3d MB\r", k / 1024);
272 memset(mem, 0xaaaaaaaa, 1024);
273 for (n = 0; n < kend; ++n) {
274 if (mem[n] != 0xaaaaaaaa) {
275 printf("SDRAM test fails at: %08x\n",
281 memset(mem, 0x55555555, 1024);
282 for (n = 0; n < kend; ++n) {
283 if (mem[n] != 0x55555555) {
284 printf("SDRAM test fails at: %08x\n",
290 printf("SDRAM test passes\n");
295 /*************************************************************************
298 * This routine is called just prior to registering the hose and gives
299 * the board the opportunity to check things. Returning a value of zero
300 * indicates that things are bad & PCI initialization should be aborted.
302 * Different boards may wish to customize the pci controller structure
303 * (add regions, override default access routines, etc) or perform
304 * certain pre-initialization actions.
306 ************************************************************************/
307 #if defined(CONFIG_PCI)
308 int pci_pre_init(struct pci_controller *hose)
312 /*-------------------------------------------------------------------------+
313 | Set priority for all PLB3 devices to 0.
314 | Set PLB3 arbiter to fair mode.
315 +-------------------------------------------------------------------------*/
316 mfsdr(sdr_amp1, addr);
317 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
318 addr = mfdcr(plb3_acr);
319 mtdcr(plb3_acr, addr | 0x80000000);
321 /*-------------------------------------------------------------------------+
322 | Set priority for all PLB4 devices to 0.
323 +-------------------------------------------------------------------------*/
324 mfsdr(sdr_amp0, addr);
325 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
326 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
327 mtdcr(plb4_acr, addr);
329 /*-------------------------------------------------------------------------+
330 | Set Nebula PLB4 arbiter to fair mode.
331 +-------------------------------------------------------------------------*/
333 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
334 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
335 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
336 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
337 mtdcr(plb0_acr, addr);
340 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
341 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
342 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
343 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
344 mtdcr(plb1_acr, addr);
348 #endif /* defined(CONFIG_PCI) */
350 /*************************************************************************
353 * The bootstrap configuration provides default settings for the pci
354 * inbound map (PIM). But the bootstrap config choices are limited and
355 * may not be sufficient for a given board.
357 ************************************************************************/
358 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
359 void pci_target_init(struct pci_controller *hose)
361 /*--------------------------------------------------------------------------+
362 * Set up Direct MMIO registers
363 *--------------------------------------------------------------------------*/
364 /*--------------------------------------------------------------------------+
365 | PowerPC440EPX PCI Master configuration.
366 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
367 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
368 | Use byte reversed out routines to handle endianess.
369 | Make this region non-prefetchable.
370 +--------------------------------------------------------------------------*/
371 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
372 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
373 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
374 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
375 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
377 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
378 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
379 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
380 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
381 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
383 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
384 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
385 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
386 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
388 /*--------------------------------------------------------------------------+
389 * Set up Configuration registers
390 *--------------------------------------------------------------------------*/
392 /* Program the board's subsystem id/vendor id */
393 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
394 CFG_PCI_SUBSYS_VENDORID);
395 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
397 /* Configure command register as bus master */
398 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
400 /* 240nS PCI clock */
401 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
403 /* No error reporting */
404 pci_write_config_word(0, PCI_ERREN, 0);
406 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
409 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
411 /*************************************************************************
414 ************************************************************************/
415 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
416 void pci_master_init(struct pci_controller *hose)
418 unsigned short temp_short;
420 /*--------------------------------------------------------------------------+
421 | Write the PowerPC440 EP PCI Configuration regs.
422 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
423 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
424 +--------------------------------------------------------------------------*/
425 pci_read_config_word(0, PCI_COMMAND, &temp_short);
426 pci_write_config_word(0, PCI_COMMAND,
427 temp_short | PCI_COMMAND_MASTER |
430 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
432 /*************************************************************************
435 * This routine is called to determine if a pci scan should be
436 * performed. With various hardware environments (especially cPCI and
437 * PPMC) it's insufficient to depend on the state of the arbiter enable
438 * bit in the strap register, or generic host/adapter assumptions.
440 * Rather than hard-code a bad assumption in the general 440 code, the
441 * 440 pci code requires the board to decide at runtime.
443 * Return 0 for adapter mode, non-zero for host (monarch) mode.
446 ************************************************************************/
447 #if defined(CONFIG_PCI)
448 int is_pci_host(struct pci_controller *hose)
450 /* Cactus is always configured as host. */
453 #endif /* defined(CONFIG_PCI) */
455 void hw_watchdog_reset(void)
460 * Toggle watchdog output
462 val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
463 gpio_write_bit(CFG_GPIO_WATCHDOG, val);