2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License as
4 * published by the Free Software Foundation; either version 2 of
5 * the License, or (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #include <asm/arch/hardware.h>
25 * Control Registers in Bank 0
28 #define CTL_REG_ERDPTL 0x00
29 #define CTL_REG_ERDPTH 0x01
30 #define CTL_REG_EWRPTL 0x02
31 #define CTL_REG_EWRPTH 0x03
32 #define CTL_REG_ETXSTL 0x04
33 #define CTL_REG_ETXSTH 0x05
34 #define CTL_REG_ETXNDL 0x06
35 #define CTL_REG_ETXNDH 0x07
36 #define CTL_REG_ERXSTL 0x08
37 #define CTL_REG_ERXSTH 0x09
38 #define CTL_REG_ERXNDL 0x0A
39 #define CTL_REG_ERXNDA 0x0B
40 #define CTL_REG_ERXRDPTL 0x0C
41 #define CTL_REG_ERXRDPTH 0x0D
42 #define CTL_REG_ERXWRPTL 0x0E
43 #define CTL_REG_ERXWRPTH 0x0F
44 #define CTL_REG_EDMASTL 0x10
45 #define CTL_REG_EDMASTH 0x11
46 #define CTL_REG_EDMANDL 0x12
47 #define CTL_REG_EDMANDH 0x13
48 #define CTL_REG_EDMADSTL 0x14
49 #define CTL_REG_EDMADSTH 0x15
50 #define CTL_REG_EDMACSL 0x16
51 #define CTL_REG_EDMACSH 0x17
52 /* these are common in all banks */
53 #define CTL_REG_EIE 0x1B
54 #define CTL_REG_EIR 0x1C
55 #define CTL_REG_ESTAT 0x1D
56 #define CTL_REG_ECON2 0x1E
57 #define CTL_REG_ECON1 0x1F
60 * Control Registers in Bank 1
63 #define CTL_REG_EHT0 0x00
64 #define CTL_REG_EHT1 0x01
65 #define CTL_REG_EHT2 0x02
66 #define CTL_REG_EHT3 0x03
67 #define CTL_REG_EHT4 0x04
68 #define CTL_REG_EHT5 0x05
69 #define CTL_REG_EHT6 0x06
70 #define CTL_REG_EHT7 0x07
71 #define CTL_REG_EPMM0 0x08
72 #define CTL_REG_EPMM1 0x09
73 #define CTL_REG_EPMM2 0x0A
74 #define CTL_REG_EPMM3 0x0B
75 #define CTL_REG_EPMM4 0x0C
76 #define CTL_REG_EPMM5 0x0D
77 #define CTL_REG_EPMM6 0x0E
78 #define CTL_REG_EPMM7 0x0F
79 #define CTL_REG_EPMCSL 0x10
80 #define CTL_REG_EPMCSH 0x11
81 #define CTL_REG_EPMOL 0x14
82 #define CTL_REG_EPMOH 0x15
83 #define CTL_REG_EWOLIE 0x16
84 #define CTL_REG_EWOLIR 0x17
85 #define CTL_REG_ERXFCON 0x18
86 #define CTL_REG_EPKTCNT 0x19
89 * Control Registers in Bank 2
92 #define CTL_REG_MACON1 0x00
93 #define CTL_REG_MACON2 0x01
94 #define CTL_REG_MACON3 0x02
95 #define CTL_REG_MACON4 0x03
96 #define CTL_REG_MABBIPG 0x04
97 #define CTL_REG_MAIPGL 0x06
98 #define CTL_REG_MAIPGH 0x07
99 #define CTL_REG_MACLCON1 0x08
100 #define CTL_REG_MACLCON2 0x09
101 #define CTL_REG_MAMXFLL 0x0A
102 #define CTL_REG_MAMXFLH 0x0B
103 #define CTL_REG_MAPHSUP 0x0D
104 #define CTL_REG_MICON 0x11
105 #define CTL_REG_MICMD 0x12
106 #define CTL_REG_MIREGADR 0x14
107 #define CTL_REG_MIWRL 0x16
108 #define CTL_REG_MIWRH 0x17
109 #define CTL_REG_MIRDL 0x18
110 #define CTL_REG_MIRDH 0x19
113 * Control Registers in Bank 3
116 #define CTL_REG_MAADR1 0x00
117 #define CTL_REG_MAADR0 0x01
118 #define CTL_REG_MAADR3 0x02
119 #define CTL_REG_MAADR2 0x03
120 #define CTL_REG_MAADR5 0x04
121 #define CTL_REG_MAADR4 0x05
122 #define CTL_REG_EBSTSD 0x06
123 #define CTL_REG_EBSTCON 0x07
124 #define CTL_REG_EBSTCSL 0x08
125 #define CTL_REG_EBSTCSH 0x09
126 #define CTL_REG_MISTAT 0x0A
127 #define CTL_REG_EREVID 0x12
128 #define CTL_REG_ECOCON 0x15
129 #define CTL_REG_EFLOCON 0x17
130 #define CTL_REG_EPAUSL 0x18
131 #define CTL_REG_EPAUSH 0x19
138 #define PHY_REG_PHID1 0x02
139 #define PHY_REG_PHID2 0x03
143 * Receive Filter Register (ERXFCON) bits
146 #define ENC_RFR_UCEN 0x80
147 #define ENC_RFR_ANDOR 0x40
148 #define ENC_RFR_CRCEN 0x20
149 #define ENC_RFR_PMEN 0x10
150 #define ENC_RFR_MPEN 0x08
151 #define ENC_RFR_HTEN 0x04
152 #define ENC_RFR_MCEN 0x02
153 #define ENC_RFR_BCEN 0x01
156 * ECON1 Register Bits
159 #define ENC_ECON1_TXRST 0x80
160 #define ENC_ECON1_RXRST 0x40
161 #define ENC_ECON1_DMAST 0x20
162 #define ENC_ECON1_CSUMEN 0x10
163 #define ENC_ECON1_TXRTS 0x08
164 #define ENC_ECON1_RXEN 0x04
165 #define ENC_ECON1_BSEL1 0x02
166 #define ENC_ECON1_BSEL0 0x01
169 * ECON2 Register Bits
171 #define ENC_ECON2_AUTOINC 0x80
172 #define ENC_ECON2_PKTDEC 0x40
173 #define ENC_ECON2_PWRSV 0x20
174 #define ENC_ECON2_VRPS 0x08
179 #define ENC_EIR_PKTIF 0x40
180 #define ENC_EIR_DMAIF 0x20
181 #define ENC_EIR_LINKIF 0x10
182 #define ENC_EIR_TXIF 0x08
183 #define ENC_EIR_WOLIF 0x04
184 #define ENC_EIR_TXERIF 0x02
185 #define ENC_EIR_RXERIF 0x01
188 * ESTAT Register Bits
191 #define ENC_ESTAT_INT 0x80
192 #define ENC_ESTAT_LATECOL 0x10
193 #define ENC_ESTAT_RXBUSY 0x04
194 #define ENC_ESTAT_TXABRT 0x02
195 #define ENC_ESTAT_CLKRDY 0x01
201 #define ENC_EIE_INTIE 0x80
202 #define ENC_EIE_PKTIE 0x40
203 #define ENC_EIE_DMAIE 0x20
204 #define ENC_EIE_LINKIE 0x10
205 #define ENC_EIE_TXIE 0x08
206 #define ENC_EIE_WOLIE 0x04
207 #define ENC_EIE_TXERIE 0x02
208 #define ENC_EIE_RXERIE 0x01
211 * MACON1 Register Bits
213 #define ENC_MACON1_LOOPBK 0x10
214 #define ENC_MACON1_TXPAUS 0x08
215 #define ENC_MACON1_RXPAUS 0x04
216 #define ENC_MACON1_PASSALL 0x02
217 #define ENC_MACON1_MARXEN 0x01
221 * MACON2 Register Bits
223 #define ENC_MACON2_MARST 0x80
224 #define ENC_MACON2_RNDRST 0x40
225 #define ENC_MACON2_MARXRST 0x08
226 #define ENC_MACON2_RFUNRST 0x04
227 #define ENC_MACON2_MATXRST 0x02
228 #define ENC_MACON2_TFUNRST 0x01
231 * MACON3 Register Bits
233 #define ENC_MACON3_PADCFG2 0x80
234 #define ENC_MACON3_PADCFG1 0x40
235 #define ENC_MACON3_PADCFG0 0x20
236 #define ENC_MACON3_TXCRCEN 0x10
237 #define ENC_MACON3_PHDRLEN 0x08
238 #define ENC_MACON3_HFRMEN 0x04
239 #define ENC_MACON3_FRMLNEN 0x02
240 #define ENC_MACON3_FULDPX 0x01
243 * MICMD Register Bits
245 #define ENC_MICMD_MIISCAN 0x02
246 #define ENC_MICMD_MIIRD 0x01
249 * MISTAT Register Bits
251 #define ENC_MISTAT_NVALID 0x04
252 #define ENC_MISTAT_SCAN 0x02
253 #define ENC_MISTAT_BUSY 0x01
256 * PHID1 and PHID2 values
258 #define ENC_PHID1_VALUE 0x0083
259 #define ENC_PHID2_VALUE 0x1400
260 #define ENC_PHID2_MASK 0xFC00
263 #define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */
264 #define ENC_RESET 0x00020000 /* pin P1.17 */
266 #define FAILSAFE_VALUE 5000
269 * Controller memory layout:
271 * 0x0000 - 0x17ff 6k bytes receive buffer
272 * 0x1800 - 0x1fff 2k bytes transmit buffer
274 /* Use the lower memory for receiver buffer. See errata pt. 5 */
275 #define ENC_RX_BUF_START 0x0000
276 #define ENC_TX_BUF_START 0x1800
278 /* maximum frame length */
279 #define ENC_MAX_FRM_LEN 1518
281 #define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
282 #define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
283 #define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
286 static unsigned char encReadReg(unsigned char regNo);
287 static void encWriteReg(unsigned char regNo, unsigned char data);
288 static void encWriteRegRetry(unsigned char regNo, unsigned char data, int c);
289 static void encReadBuff(unsigned short length, unsigned char *pBuff);
290 static void encWriteBuff(unsigned short length, unsigned char *pBuff);
291 static void encBitSet(unsigned char regNo, unsigned char data);
292 static void encBitClr(unsigned char regNo, unsigned char data);
293 static void encReset(void);
294 static void encInit(unsigned char *pEthAddr);
295 static unsigned short phyRead(unsigned char addr);
296 static void encPoll(void);
297 static void encRx(void);
299 #define m_nic_read(reg) encReadReg(reg)
300 #define m_nic_write(reg, data) encWriteReg(reg, data)
301 #define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count)
302 #define m_nic_read_data(len, buf) encReadBuff((len), (buf))
303 #define m_nic_write_data(len, buf) encWriteBuff((len), (buf))
306 #define m_nic_bfs(reg, data) encBitSet(reg, data)
308 /* bit field clear */
309 #define m_nic_bfc(reg, data) encBitClr(reg, data)
311 static unsigned char bank = 0; /* current bank in enc28j60 */
312 static unsigned char next_pointer_lsb;
313 static unsigned char next_pointer_msb;
315 static unsigned char buffer[ENC_MAX_FRM_LEN];
316 static int rxResetCounter = 0;
317 #define RX_RESET_COUNTER 1000;
319 /*-----------------------------------------------------------------------------
320 * Returns 0 when failes otherwize 1
322 int eth_init(bd_t *bis)
325 (*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
326 (*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
328 /* CS and RESET active low */
329 PUT32(IO1SET, ENC_SPI_SLAVE_CS);
330 PUT32(IO1SET, ENC_RESET);
334 /* initialize controller */
336 encInit(bis->bi_enetaddr);
338 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
343 int eth_send(volatile void *packet, int length)
345 /* check frame length, etc. */
348 /* switch to bank 0 */
349 m_nic_bfc(CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
352 m_nic_write(CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
353 m_nic_write(CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
356 m_nic_write(CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
357 m_nic_write(CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
360 m_nic_write_data(length, (unsigned char*)packet);
363 m_nic_write(CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
364 m_nic_write(CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
366 /* set ECON1.TXRTS */
367 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRTS);
373 /*****************************************************************************
374 * This function resets the receiver only. This function may be called from
377 static void encReceiverReset(void)
381 econ1 = m_nic_read(CTL_REG_ECON1);
382 if((econ1 & ENC_ECON1_RXRST) == 0) {
383 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_RXRST);
384 rxResetCounter = RX_RESET_COUNTER;
388 /*****************************************************************************
389 * receiver reset timer
391 static void encReceiverResetCallback(void)
393 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_RXRST);
394 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
397 /*-----------------------------------------------------------------------------
398 * Check for received packets. Call NetReceive for each packet. The return
399 * value is ignored by the caller.
403 if(rxResetCounter > 0 && --rxResetCounter == 0)
405 encReceiverResetCallback();
415 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */
418 /*****************************************************************************/
420 static void encPoll(void)
422 unsigned char eir_reg;
423 volatile unsigned char estat_reg;
424 unsigned char pkt_cnt;
426 /* clear global interrupt enable bit in enc28j60 */
427 m_nic_bfc(CTL_REG_EIE, ENC_EIE_INTIE);
428 estat_reg = m_nic_read(CTL_REG_ESTAT);
430 eir_reg = m_nic_read(CTL_REG_EIR);
432 if (eir_reg & ENC_EIR_TXIF){
433 /* clear TXIF bit in EIR */
434 m_nic_bfc(CTL_REG_EIR, ENC_EIR_TXIF);
437 /* We have to use pktcnt and not pktif bit, see errata pt. 6 */
440 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL1);
441 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
444 pkt_cnt = m_nic_read(CTL_REG_EPKTCNT);
447 if ((eir_reg & ENC_EIR_PKTIF) == 0) {
448 /*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */
451 /* clear PKTIF bit in EIR, this should not need to be done but it
452 seems like we get problems if we do not */
453 m_nic_bfc(CTL_REG_EIR, ENC_EIR_PKTIF);
456 if (eir_reg & ENC_EIR_RXERIF) {
457 printf("encPoll: rx error\n");
458 m_nic_bfc(CTL_REG_EIR, ENC_EIR_RXERIF);
460 if (eir_reg & ENC_EIR_TXERIF) {
461 printf("encPoll: tx error\n");
462 m_nic_bfc(CTL_REG_EIR, ENC_EIR_TXERIF);
465 /* set global interrupt enable bit in enc28j60 */
466 m_nic_bfs(CTL_REG_EIE, ENC_EIE_INTIE);
469 static void encRx(void)
471 unsigned short pkt_len;
472 unsigned short copy_len;
473 unsigned short status;
474 unsigned char eir_reg;
475 unsigned char pkt_cnt = 0;
477 /* switch to bank 0 */
478 m_nic_bfc(CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
480 m_nic_write(CTL_REG_ERDPTL, next_pointer_lsb);
481 m_nic_write(CTL_REG_ERDPTH, next_pointer_msb);
484 m_nic_read_data(6, buffer);
485 next_pointer_lsb = buffer[0];
486 next_pointer_msb = buffer[1];
488 pkt_len |= (unsigned short)buffer[3] << 8;
490 status |= (unsigned short)buffer[5] << 8;
492 if (pkt_len <= ENC_MAX_FRM_LEN) {
496 /* p_priv->stats.rx_dropped++; */
497 /* we will drop this packet */
500 if ((status & (1L << 7)) == 0) { /* check Received Ok bit */
502 /* p_priv->stats.rx_errors++; */
506 m_nic_read_data(copy_len, buffer);
509 /* advance read pointer to next pointer */
510 m_nic_write(CTL_REG_ERDPTL, next_pointer_lsb);
511 m_nic_write(CTL_REG_ERDPTH, next_pointer_msb);
513 /* decrease packet counter */
514 m_nic_bfs(CTL_REG_ECON2, ENC_ECON2_PKTDEC);
517 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL1);
518 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
521 pkt_cnt = m_nic_read(CTL_REG_EPKTCNT);
523 /* switch to bank 0 */
524 m_nic_bfc(CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
527 eir_reg = m_nic_read(CTL_REG_EIR);
529 printf("eth_rx: copy_len=0\n");
533 NetReceive((unsigned char *)buffer, pkt_len);
535 eir_reg = m_nic_read(CTL_REG_EIR);
536 } while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
537 m_nic_write(CTL_REG_ERXRDPTL, next_pointer_lsb);
538 m_nic_write(CTL_REG_ERXRDPTH, next_pointer_msb);
541 static void encWriteReg(unsigned char regNo, unsigned char data)
547 spi_write(0x40 | regNo); /* write in regNo */
553 spi_write(0x1f); /* write reg 0x1f */
559 static void encWriteRegRetry(unsigned char regNo, unsigned char data, int c)
561 unsigned char readback;
566 for (i = 0; i < c; i++) {
570 spi_write(0x40 | regNo); /* write in regNo */
576 spi_write(0x1f); /* write reg 0x1f */
580 spi_unlock(); /* we must unlock spi first */
582 readback = encReadReg(regNo);
586 if (readback == data)
592 printf("enc28j60: write reg %d failed\n", regNo);
596 static unsigned char encReadReg(unsigned char regNo)
598 unsigned char rxByte;
604 spi_write(0x1f); /* read reg 0x1f */
606 bank = spi_read() & 0x3;
614 /* check if MAC or MII register */
615 if (((bank == 2) && (regNo <= 0x1a)) ||
616 ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) {
617 /* ignore first byte and read another byte */
627 static void encReadBuff(unsigned short length, unsigned char *pBuff)
633 spi_write(0x20 | 0x1a); /* read buffer memory */
637 *pBuff++ = spi_read();
646 static void encWriteBuff(unsigned short length,
647 unsigned char *pBuff)
653 spi_write(0x60 | 0x1a); /* write buffer memory */
655 spi_write(0x00); /* control byte */
664 static void encBitSet(unsigned char regNo, unsigned char data)
670 spi_write(0x80 | regNo); /* bit field set */
677 static void encBitClr(unsigned char regNo, unsigned char data)
683 spi_write(0xA0 | regNo); /* bit field clear */
690 static void encReset(void)
696 spi_write(0xff); /* soft reset */
701 /* sleep 1 ms. See errata pt. 2 */
705 (*((volatile unsigned long*)IO1CLR)) &= ENC_RESET;
707 (*((volatile unsigned long*)IO1SET)) &= ENC_RESET;
711 static void encInit(unsigned char *pEthAddr)
713 unsigned short phid1 = 0;
714 unsigned short phid2 = 0;
716 /* switch to bank 0 */
717 m_nic_bfc(CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
720 * Setup the buffer space. The reset values are valid for the
724 /* We shall not write to ERXST, see errata pt. 5. Instead we
725 have to make sure that ENC_RX_BUS_START is 0. */
726 m_nic_write_retry(CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
727 m_nic_write_retry(CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
729 m_nic_write_retry(CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
730 m_nic_write_retry(CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
732 next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
733 next_pointer_msb = (ENC_RX_BUF_START >> 8);
736 * For tracking purposes, the ERXRDPT registers should be programmed with
737 * the same value. This is the read pointer.
739 m_nic_write(CTL_REG_ERXRDPTL, (ENC_RX_BUF_START & 0xFF));
740 m_nic_write_retry(CTL_REG_ERXRDPTH, (ENC_RX_BUF_START >> 8), 1);
742 /* Setup receive filters. */
745 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL1);
746 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
748 /* OR-filtering, Unicast, CRC-check and broadcast */
749 m_nic_write_retry(CTL_REG_ERXFCON,
750 (ENC_RFR_UCEN|ENC_RFR_CRCEN|ENC_RFR_BCEN), 1);
752 /* Wait for Oscillator Start-up Timer (OST). */
753 while((m_nic_read(CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) == 0) {
760 /* verify identification */
761 phid1 = phyRead(PHY_REG_PHID1);
762 phid2 = phyRead(PHY_REG_PHID2);
764 if(phid1 != ENC_PHID1_VALUE
765 || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) {
766 printf("ERROR: failed to identify controller\n");
767 printf("phid1 = %x, phid2 = %x\n",
768 phid1, (phid2&ENC_PHID2_MASK));
769 printf("should be phid1 = %x, phid2 = %x\n",
770 ENC_PHID1_VALUE, ENC_PHID2_VALUE);
774 * --- MAC Initialization ---
777 /* Pull MAC out of Reset */
779 /* switch to bank 2 */
780 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
781 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
782 /* clear MAC reset bits */
783 m_nic_write_retry(CTL_REG_MACON2, 0, 1);
785 /* enable MAC to receive frames */
786 m_nic_write_retry(CTL_REG_MACON1, ENC_MACON1_MARXEN, 10);
788 /* configure pad, tx-crc and duplex */
789 /* TODO maybe enable FRMLNEN */
790 m_nic_write_retry(CTL_REG_MACON3, (ENC_MACON3_PADCFG0|ENC_MACON3_TXCRCEN),
793 /* set maximum frame length */
794 m_nic_write_retry(CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
795 m_nic_write_retry(CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10);
798 * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex
799 * and 0x15 for full duplex.
801 m_nic_write_retry(CTL_REG_MABBIPG, 0x12, 10);
803 /* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
804 m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10);
807 * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
808 * 0x0c for half-duplex. Nothing for full-duplex
810 m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10);
812 /* set MAC address */
814 /* switch to bank 3 */
815 m_nic_bfs(CTL_REG_ECON1, (ENC_ECON1_BSEL0|ENC_ECON1_BSEL1));
817 m_nic_write_retry(CTL_REG_MAADR0, pEthAddr[5], 1);
818 m_nic_write_retry(CTL_REG_MAADR1, pEthAddr[4], 1);
819 m_nic_write_retry(CTL_REG_MAADR2, pEthAddr[3], 1);
820 m_nic_write_retry(CTL_REG_MAADR3, pEthAddr[2], 1);
821 m_nic_write_retry(CTL_REG_MAADR4, pEthAddr[1], 1);
822 m_nic_write_retry(CTL_REG_MAADR5, pEthAddr[0], 1);
828 /* auto-increment RX-pointer when reading a received packet */
829 m_nic_bfs(CTL_REG_ECON2, ENC_ECON2_AUTOINC);
831 /* enable interrupts */
832 m_nic_bfs(CTL_REG_EIE, ENC_EIE_PKTIE);
833 m_nic_bfs(CTL_REG_EIE, ENC_EIE_TXIE);
834 m_nic_bfs(CTL_REG_EIE, ENC_EIE_RXERIE);
835 m_nic_bfs(CTL_REG_EIE, ENC_EIE_TXERIE);
836 m_nic_bfs(CTL_REG_EIE, ENC_EIE_INTIE);
839 /*****************************************************************************
842 * Read PHY registers.
844 * NOTE! This function will change to Bank 2.
847 * [in] addr address of the register to read
850 * The value in the register
852 static unsigned short phyRead(unsigned char addr)
854 unsigned short ret = 0;
857 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
858 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
860 /* write address to MIREGADR */
861 m_nic_write(CTL_REG_MIREGADR, addr);
863 /* set MICMD.MIIRD */
864 m_nic_write(CTL_REG_MICMD, ENC_MICMD_MIIRD);
866 /* poll MISTAT.BUSY bit until operation is complete */
867 while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
871 /* GJ - this seems extremely dangerous! */
877 /* clear MICMD.MIIRD */
878 m_nic_write(CTL_REG_MICMD, 0);
880 ret = (m_nic_read(CTL_REG_MIRDH) << 8);
881 ret |= (m_nic_read(CTL_REG_MIRDL) & 0xFF);