1 // SPDX-License-Identifier: GPL-2.0+
4 * Logic Product Development <www.logicpd.com>
7 * Peter Barada <peter.barada@logicpd.com>
9 * Derived from Beagle Board and 3430 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
25 #include <asm/arch/mmc_host_def.h>
26 #include <asm/arch/mux.h>
27 #include <asm/arch/mem.h>
28 #include <asm/arch/sys_proto.h>
30 #include <asm/omap_mmc.h>
31 #include <asm/mach-types.h>
32 #include <linux/mtd/rawnand.h>
33 #include <asm/omap_musb.h>
34 #include <linux/errno.h>
35 #include <linux/usb/ch9.h>
36 #include <linux/usb/gadget.h>
37 #include <linux/usb/musb.h>
38 #include "omap3logic.h"
39 #ifdef CONFIG_USB_EHCI_HCD
41 #include <asm/ehci-omap.h>
44 DECLARE_GLOBAL_DATA_PTR;
46 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203
47 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302
48 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302
49 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303
50 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18
51 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000
52 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50
54 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203
55 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102
56 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102
57 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103
58 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15
59 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
60 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
62 #ifdef CONFIG_SPL_OS_BOOT
63 int spl_start_uboot(void)
65 /* break into full u-boot on 'c' */
66 return serial_tstc() && serial_getc() == 'c';
70 #if defined(CONFIG_SPL_BUILD)
72 * Routine: get_board_mem_timings
73 * Description: If we use SPL then there is no x-loader nor config header
74 * so we have to setup the DDR timings ourself on the first bank. This
75 * provides the timing values back to the function that configures
78 void get_board_mem_timings(struct board_sdrc_timings *timings)
80 timings->mr = MICRON_V_MR_165;
82 if (get_cpu_family() == CPU_OMAP36XX) {
83 /* 200 MHz works for OMAP36/DM37 */
85 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
86 timings->ctrla = MICRON_V_ACTIMA_200;
87 timings->ctrlb = MICRON_V_ACTIMB_200;
88 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
90 /* 165 MHz works for OMAP35 */
91 timings->mcfg = MICRON_V_MCFG_165(256 << 20);
92 timings->ctrla = MICRON_V_ACTIMA_165;
93 timings->ctrlb = MICRON_V_ACTIMB_165;
94 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
98 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
99 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
100 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
102 void spl_board_prepare_for_linux(void)
104 /* The Micron NAND starts locked which
105 * prohibits mounting the NAND as RW
106 * The following commands are what unlocks
107 * the NAND to become RW Falcon Mode does not
108 * have as many smarts as U-Boot, but Logic PD
109 * only makes NAND with 512MB so these hard coded
110 * values should work for all current models
113 writeb(0x70, GPMC_NAND_COMMAND_0);
114 writeb(-1, GPMC_NAND_DATA_0);
115 writeb(0x7a, GPMC_NAND_COMMAND_0);
116 writeb(0x00, GPMC_NAND_ADDRESS_0);
117 writeb(0x00, GPMC_NAND_ADDRESS_0);
118 writeb(0x00, GPMC_NAND_ADDRESS_0);
119 writeb(-1, GPMC_NAND_COMMAND_0);
121 /* Begin address 0 */
122 writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
123 writeb(0x00, GPMC_NAND_ADDRESS_0);
124 writeb(0x00, GPMC_NAND_ADDRESS_0);
125 writeb(0x00, GPMC_NAND_ADDRESS_0);
126 writeb(-1, GPMC_NAND_DATA_0);
128 /* Ending address at the end of Flash */
129 writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
130 writeb(0xc0, GPMC_NAND_ADDRESS_0);
131 writeb(0xff, GPMC_NAND_ADDRESS_0);
132 writeb(0x03, GPMC_NAND_ADDRESS_0);
133 writeb(-1, GPMC_NAND_DATA_0);
134 writeb(0x79, GPMC_NAND_COMMAND_0);
135 writeb(-1, GPMC_NAND_DATA_0);
136 writeb(-1, GPMC_NAND_DATA_0);
141 * Routine: misc_init_r
142 * Description: Configure board specific parts
144 int misc_init_r(void)
146 twl4030_power_init();
147 twl4030_power_mmc_init(0);
148 omap_die_id_display();
152 #if defined(CONFIG_FLASH_CFI_DRIVER)
153 static const u32 gpmc_dm37_c2nor_config[] = {
154 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
155 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
156 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
157 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
158 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
159 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
160 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
163 static const u32 gpmc_omap35_c2nor_config[] = {
164 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
165 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
166 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
167 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
168 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
169 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
170 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
175 * Routine: board_init
176 * Description: Early hardware init.
180 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
182 /* boot param addr */
183 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
184 #if defined(CONFIG_FLASH_CFI_DRIVER)
185 if (get_cpu_family() == CPU_OMAP36XX) {
186 /* Enable CS2 for NOR Flash */
187 enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
188 0x10000000, GPMC_SIZE_64M);
190 enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
191 0x10000000, GPMC_SIZE_64M);
197 #ifdef CONFIG_BOARD_LATE_INIT
199 static void unlock_nand(void)
201 int dev = nand_curr_device;
202 struct mtd_info *mtd;
204 mtd = get_nand_dev_by_index(dev);
205 nand_unlock(mtd, 0, mtd->size, 0);
208 int board_late_init(void)
210 #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
217 #if defined(CONFIG_MMC)
218 void board_mmc_power_init(void)
220 twl4030_power_mmc_init(0);
224 #ifdef CONFIG_SMC911X
225 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
226 static const u32 gpmc_lan92xx_config[] = {
227 NET_LAN92XX_GPMC_CONFIG1,
228 NET_LAN92XX_GPMC_CONFIG2,
229 NET_LAN92XX_GPMC_CONFIG3,
230 NET_LAN92XX_GPMC_CONFIG4,
231 NET_LAN92XX_GPMC_CONFIG5,
232 NET_LAN92XX_GPMC_CONFIG6,
235 int board_eth_init(bd_t *bis)
237 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
238 CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
240 return smc911x_initialize(0, CONFIG_SMC911X_BASE);