1 // SPDX-License-Identifier: GPL-2.0+
4 * Logic Product Development <www.logicpd.com>
7 * Peter Barada <peter.barada@logicpd.com>
9 * Derived from Beagle Board and 3430 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/mux.h>
24 #include <asm/arch/mem.h>
25 #include <asm/arch/sys_proto.h>
27 #include <asm/omap_mmc.h>
28 #include <asm/mach-types.h>
29 #include <linux/mtd/rawnand.h>
30 #include <asm/omap_musb.h>
31 #include <linux/errno.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/musb.h>
35 #include "omap3logic.h"
36 #ifdef CONFIG_USB_EHCI_HCD
38 #include <asm/ehci-omap.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203
44 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302
45 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302
46 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303
47 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18
48 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000
49 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50
51 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203
52 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102
53 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102
54 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103
55 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15
56 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
57 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
59 /* This is only needed until SPL gets OF support */
60 #ifdef CONFIG_SPL_BUILD
61 static const struct ns16550_platdata omap3logic_serial = {
62 .base = OMAP34XX_UART1,
64 .clock = V_NS16550_CLK,
65 .fcr = UART_FCR_DEFVAL,
68 U_BOOT_DEVICE(omap3logic_uart) = {
73 static const struct omap_hsmmc_plat omap3_logic_mmc0_platdata = {
74 .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
75 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
77 .cfg.f_max = 52000000,
78 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
79 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
82 U_BOOT_DEVICE(omap3_logic_mmc0) = {
84 .platdata = &omap3_logic_mmc0_platdata,
89 #ifdef CONFIG_SPL_OS_BOOT
90 int spl_start_uboot(void)
92 /* break into full u-boot on 'c' */
93 return serial_tstc() && serial_getc() == 'c';
97 #if defined(CONFIG_SPL_BUILD)
99 * Routine: get_board_mem_timings
100 * Description: If we use SPL then there is no x-loader nor config header
101 * so we have to setup the DDR timings ourself on the first bank. This
102 * provides the timing values back to the function that configures
105 void get_board_mem_timings(struct board_sdrc_timings *timings)
107 timings->mr = MICRON_V_MR_165;
109 if (get_cpu_family() == CPU_OMAP36XX) {
110 /* 200 MHz works for OMAP36/DM37 */
112 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
113 timings->ctrla = MICRON_V_ACTIMA_200;
114 timings->ctrlb = MICRON_V_ACTIMB_200;
115 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
117 /* 165 MHz works for OMAP35 */
118 timings->mcfg = MICRON_V_MCFG_165(256 << 20);
119 timings->ctrla = MICRON_V_ACTIMA_165;
120 timings->ctrlb = MICRON_V_ACTIMB_165;
121 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
125 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
126 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
127 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
129 void spl_board_prepare_for_linux(void)
131 /* The Micron NAND starts locked which
132 * prohibits mounting the NAND as RW
133 * The following commands are what unlocks
134 * the NAND to become RW Falcon Mode does not
135 * have as many smarts as U-Boot, but Logic PD
136 * only makes NAND with 512MB so these hard coded
137 * values should work for all current models
140 writeb(0x70, GPMC_NAND_COMMAND_0);
141 writeb(-1, GPMC_NAND_DATA_0);
142 writeb(0x7a, GPMC_NAND_COMMAND_0);
143 writeb(0x00, GPMC_NAND_ADDRESS_0);
144 writeb(0x00, GPMC_NAND_ADDRESS_0);
145 writeb(0x00, GPMC_NAND_ADDRESS_0);
146 writeb(-1, GPMC_NAND_COMMAND_0);
148 /* Begin address 0 */
149 writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
150 writeb(0x00, GPMC_NAND_ADDRESS_0);
151 writeb(0x00, GPMC_NAND_ADDRESS_0);
152 writeb(0x00, GPMC_NAND_ADDRESS_0);
153 writeb(-1, GPMC_NAND_DATA_0);
155 /* Ending address at the end of Flash */
156 writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
157 writeb(0xc0, GPMC_NAND_ADDRESS_0);
158 writeb(0xff, GPMC_NAND_ADDRESS_0);
159 writeb(0x03, GPMC_NAND_ADDRESS_0);
160 writeb(-1, GPMC_NAND_DATA_0);
161 writeb(0x79, GPMC_NAND_COMMAND_0);
162 writeb(-1, GPMC_NAND_DATA_0);
163 writeb(-1, GPMC_NAND_DATA_0);
168 * Routine: misc_init_r
169 * Description: Configure board specific parts
171 int misc_init_r(void)
173 twl4030_power_init();
174 omap_die_id_display();
178 #if defined(CONFIG_FLASH_CFI_DRIVER)
179 static const u32 gpmc_dm37_c2nor_config[] = {
180 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
181 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
182 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
183 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
184 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
185 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
186 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
189 static const u32 gpmc_omap35_c2nor_config[] = {
190 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
191 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
192 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
193 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
194 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
195 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
196 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
201 * Routine: board_init
202 * Description: Early hardware init.
206 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
208 /* boot param addr */
209 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
210 #if defined(CONFIG_FLASH_CFI_DRIVER)
211 if (get_cpu_family() == CPU_OMAP36XX) {
212 /* Enable CS2 for NOR Flash */
213 enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
214 0x10000000, GPMC_SIZE_64M);
216 enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
217 0x10000000, GPMC_SIZE_64M);
223 #ifdef CONFIG_BOARD_LATE_INIT
225 static void unlock_nand(void)
227 int dev = nand_curr_device;
228 struct mtd_info *mtd;
230 mtd = get_nand_dev_by_index(dev);
231 nand_unlock(mtd, 0, mtd->size, 0);
234 int board_late_init(void)
236 #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
243 #if defined(CONFIG_MMC)
244 void board_mmc_power_init(void)
246 twl4030_power_mmc_init(0);
250 #ifdef CONFIG_SMC911X
251 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
252 static const u32 gpmc_lan92xx_config[] = {
253 NET_LAN92XX_GPMC_CONFIG1,
254 NET_LAN92XX_GPMC_CONFIG2,
255 NET_LAN92XX_GPMC_CONFIG3,
256 NET_LAN92XX_GPMC_CONFIG4,
257 NET_LAN92XX_GPMC_CONFIG5,
258 NET_LAN92XX_GPMC_CONFIG6,
261 int board_eth_init(bd_t *bis)
263 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
264 CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
266 return smc911x_initialize(0, CONFIG_SMC911X_BASE);