1 // SPDX-License-Identifier: GPL-2.0+
4 * Logic Product Development <www.logicpd.com>
7 * Peter Barada <peter.barada@logicpd.com>
9 * Derived from Beagle Board and 3430 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
24 #include <asm/arch/mmc_host_def.h>
25 #include <asm/arch/mux.h>
26 #include <asm/arch/mem.h>
27 #include <asm/arch/sys_proto.h>
29 #include <asm/omap_mmc.h>
30 #include <asm/mach-types.h>
31 #include <linux/mtd/rawnand.h>
32 #include <asm/omap_musb.h>
33 #include <linux/errno.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/musb.h>
37 #include "omap3logic.h"
38 #ifdef CONFIG_USB_EHCI_HCD
40 #include <asm/ehci-omap.h>
43 DECLARE_GLOBAL_DATA_PTR;
45 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203
46 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302
47 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302
48 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303
49 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18
50 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000
51 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50
53 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203
54 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102
55 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102
56 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103
57 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15
58 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
59 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
61 #ifdef CONFIG_SPL_OS_BOOT
62 int spl_start_uboot(void)
64 /* break into full u-boot on 'c' */
65 return serial_tstc() && serial_getc() == 'c';
69 #if defined(CONFIG_SPL_BUILD)
71 * Routine: get_board_mem_timings
72 * Description: If we use SPL then there is no x-loader nor config header
73 * so we have to setup the DDR timings ourself on the first bank. This
74 * provides the timing values back to the function that configures
77 void get_board_mem_timings(struct board_sdrc_timings *timings)
79 timings->mr = MICRON_V_MR_165;
81 if (get_cpu_family() == CPU_OMAP36XX) {
82 /* 200 MHz works for OMAP36/DM37 */
84 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
85 timings->ctrla = MICRON_V_ACTIMA_200;
86 timings->ctrlb = MICRON_V_ACTIMB_200;
87 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
89 /* 165 MHz works for OMAP35 */
90 timings->mcfg = MICRON_V_MCFG_165(256 << 20);
91 timings->ctrla = MICRON_V_ACTIMA_165;
92 timings->ctrlb = MICRON_V_ACTIMB_165;
93 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
97 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
98 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
99 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
101 void spl_board_prepare_for_linux(void)
103 /* The Micron NAND starts locked which
104 * prohibits mounting the NAND as RW
105 * The following commands are what unlocks
106 * the NAND to become RW Falcon Mode does not
107 * have as many smarts as U-Boot, but Logic PD
108 * only makes NAND with 512MB so these hard coded
109 * values should work for all current models
112 writeb(0x70, GPMC_NAND_COMMAND_0);
113 writeb(-1, GPMC_NAND_DATA_0);
114 writeb(0x7a, GPMC_NAND_COMMAND_0);
115 writeb(0x00, GPMC_NAND_ADDRESS_0);
116 writeb(0x00, GPMC_NAND_ADDRESS_0);
117 writeb(0x00, GPMC_NAND_ADDRESS_0);
118 writeb(-1, GPMC_NAND_COMMAND_0);
120 /* Begin address 0 */
121 writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
122 writeb(0x00, GPMC_NAND_ADDRESS_0);
123 writeb(0x00, GPMC_NAND_ADDRESS_0);
124 writeb(0x00, GPMC_NAND_ADDRESS_0);
125 writeb(-1, GPMC_NAND_DATA_0);
127 /* Ending address at the end of Flash */
128 writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
129 writeb(0xc0, GPMC_NAND_ADDRESS_0);
130 writeb(0xff, GPMC_NAND_ADDRESS_0);
131 writeb(0x03, GPMC_NAND_ADDRESS_0);
132 writeb(-1, GPMC_NAND_DATA_0);
133 writeb(0x79, GPMC_NAND_COMMAND_0);
134 writeb(-1, GPMC_NAND_DATA_0);
135 writeb(-1, GPMC_NAND_DATA_0);
140 * Routine: misc_init_r
141 * Description: Configure board specific parts
143 int misc_init_r(void)
145 twl4030_power_init();
146 twl4030_power_mmc_init(0);
147 omap_die_id_display();
151 #if defined(CONFIG_FLASH_CFI_DRIVER)
152 static const u32 gpmc_dm37_c2nor_config[] = {
153 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
154 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
155 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
156 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
157 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
158 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
159 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
162 static const u32 gpmc_omap35_c2nor_config[] = {
163 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
164 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
165 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
166 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
167 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
168 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
169 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
174 * Routine: board_init
175 * Description: Early hardware init.
179 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
181 /* boot param addr */
182 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
183 #if defined(CONFIG_FLASH_CFI_DRIVER)
184 if (get_cpu_family() == CPU_OMAP36XX) {
185 /* Enable CS2 for NOR Flash */
186 enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
187 0x10000000, GPMC_SIZE_64M);
189 enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
190 0x10000000, GPMC_SIZE_64M);
196 #ifdef CONFIG_BOARD_LATE_INIT
198 static void unlock_nand(void)
200 int dev = nand_curr_device;
201 struct mtd_info *mtd;
203 mtd = get_nand_dev_by_index(dev);
204 nand_unlock(mtd, 0, mtd->size, 0);
207 int board_late_init(void)
209 #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
216 #if defined(CONFIG_MMC)
217 void board_mmc_power_init(void)
219 twl4030_power_mmc_init(0);
223 #ifdef CONFIG_SMC911X
224 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
225 static const u32 gpmc_lan92xx_config[] = {
226 NET_LAN92XX_GPMC_CONFIG1,
227 NET_LAN92XX_GPMC_CONFIG2,
228 NET_LAN92XX_GPMC_CONFIG3,
229 NET_LAN92XX_GPMC_CONFIG4,
230 NET_LAN92XX_GPMC_CONFIG5,
231 NET_LAN92XX_GPMC_CONFIG6,
234 int board_eth_init(bd_t *bis)
236 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
237 CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
239 return smc911x_initialize(0, CONFIG_SMC911X_BASE);