1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Logic PD, Inc.
5 * Author: Adam Ford <aford173@gmail.com>
7 * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
8 * and updates by Jagan Teki <jagan@amarulasolutions.com>
15 #include <fsl_esdhc.h>
18 #include <linux/sizes.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/crm_regs.h>
21 #include <asm/arch/iomux.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/mx6-pins.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/mach-imx/boot_mode.h>
26 #include <asm/mach-imx/iomux-v3.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
32 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
34 #define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
40 gd->ram_size = imx_ddr_size();
44 static iomux_v3_cfg_t const uart1_pads[] = {
45 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
46 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
49 static iomux_v3_cfg_t const uart2_pads[] = {
50 MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
51 MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
52 MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
53 MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
56 static iomux_v3_cfg_t const uart3_pads[] = {
57 MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
58 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
59 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
60 MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
63 static void setup_iomux_uart(void)
65 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
66 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
67 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
70 static iomux_v3_cfg_t const nand_pads[] = {
71 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
72 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
73 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
74 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
75 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
76 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
77 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
78 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
79 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
80 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
81 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
82 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
83 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
84 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
85 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
88 static void setup_nand_pins(void)
90 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
93 static int ar8031_phy_fixup(struct phy_device *phydev)
97 /* To enable AR8031 output a 125MHz clk from CLK_25M */
98 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
99 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
100 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
102 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
105 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
107 /* introduce tx clock delay */
108 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
109 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
111 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
116 int board_phy_config(struct phy_device *phydev)
118 ar8031_phy_fixup(phydev);
120 if (phydev->drv->config)
121 phydev->drv->config(phydev);
127 * Do not overwrite the console
128 * Use always serial for U-Boot console
130 int overwrite_console(void)
135 int board_early_init_f(void)
144 /* address of boot parameters */
145 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
149 int board_late_init(void)
151 env_set("board_name", "imx6logic");
154 env_set("board_rev", "MX6DQ");
155 env_set("fdt_file", "imx6q-logicpd.dtb");
161 #ifdef CONFIG_SPL_BUILD
162 #include <asm/arch/mx6-ddr.h>
163 #include <asm/arch/mx6q-ddr.h>
165 #include <linux/libfdt.h>
167 #ifdef CONFIG_SPL_OS_BOOT
168 int spl_start_uboot(void)
170 /* break into full u-boot on 'c' */
171 if (serial_tstc() && serial_getc() == 'c')
179 #define USDHC_PAD_CTRL \
180 (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
181 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
183 static iomux_v3_cfg_t const usdhc1_pads[] = {
184 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
185 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
186 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
187 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
188 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
189 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
192 static iomux_v3_cfg_t const usdhc2_pads[] = {
193 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
194 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
195 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
196 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
197 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
198 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
199 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
202 #ifdef CONFIG_FSL_ESDHC
203 struct fsl_esdhc_cfg usdhc_cfg[] = {
204 {USDHC1_BASE_ADDR}, /* SOM */
205 {USDHC2_BASE_ADDR} /* Baseboard */
208 int board_mmc_init(bd_t *bis)
210 struct src *psrc = (struct src *)SRC_BASE_ADDR;
211 unsigned int reg = readl(&psrc->sbmr1) >> 11;
213 * Upon reading BOOT_CFG register the following map is done:
214 * Bit 11 and 12 of BOOT_CFG register can determine the current
220 reg &= 0x3; /* Only care about bottom 2 bits */
224 SETUP_IOMUX_PADS(usdhc1_pads);
225 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
226 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
227 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
230 SETUP_IOMUX_PADS(usdhc2_pads);
231 usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
232 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
233 gd->arch.sdhc_clk = usdhc_cfg[1].sdhc_clk;
237 return fsl_esdhc_initialize(bis, &usdhc_cfg[reg]);
240 int board_mmc_getcd(struct mmc *mmc)
246 static void ccgr_init(void)
248 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
250 writel(0x00C03F3F, &ccm->CCGR0);
251 writel(0x0030FC03, &ccm->CCGR1);
252 writel(0x0FFFC000, &ccm->CCGR2);
253 writel(0x3FF00000, &ccm->CCGR3);
254 writel(0xFFFFF300, &ccm->CCGR4);
255 writel(0x0F0000F3, &ccm->CCGR5);
256 writel(0x00000FFF, &ccm->CCGR6);
259 static int mx6q_dcd_table[] = {
260 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
261 MX6_IOM_GRP_DDRPKE, 0x00000000,
262 MX6_IOM_DRAM_SDCLK_0, 0x00000030,
263 MX6_IOM_DRAM_SDCLK_1, 0x00000030,
264 MX6_IOM_DRAM_CAS, 0x00000030,
265 MX6_IOM_DRAM_RAS, 0x00000030,
266 MX6_IOM_GRP_ADDDS, 0x00000030,
267 MX6_IOM_DRAM_RESET, 0x00000030,
268 MX6_IOM_DRAM_SDBA2, 0x00000000,
269 MX6_IOM_DRAM_SDODT0, 0x00000030,
270 MX6_IOM_DRAM_SDODT1, 0x00000030,
271 MX6_IOM_GRP_CTLDS, 0x00000030,
272 MX6_IOM_DDRMODE_CTL, 0x00020000,
273 MX6_IOM_DRAM_SDQS0, 0x00000030,
274 MX6_IOM_DRAM_SDQS1, 0x00000030,
275 MX6_IOM_DRAM_SDQS2, 0x00000030,
276 MX6_IOM_DRAM_SDQS3, 0x00000030,
277 MX6_IOM_GRP_DDRMODE, 0x00020000,
278 MX6_IOM_GRP_B0DS, 0x00000030,
279 MX6_IOM_GRP_B1DS, 0x00000030,
280 MX6_IOM_GRP_B2DS, 0x00000030,
281 MX6_IOM_GRP_B3DS, 0x00000030,
282 MX6_IOM_DRAM_DQM0, 0x00000030,
283 MX6_IOM_DRAM_DQM1, 0x00000030,
284 MX6_IOM_DRAM_DQM2, 0x00000030,
285 MX6_IOM_DRAM_DQM3, 0x00000030,
286 MX6_MMDC_P0_MDSCR, 0x00008000,
287 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
288 MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
289 MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
290 MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
291 MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
292 MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
293 MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
294 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
295 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
296 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
297 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
298 MX6_MMDC_P0_MPMUR0, 0x00000800,
299 MX6_MMDC_P0_MDPDC, 0x00020036,
300 MX6_MMDC_P0_MDOTC, 0x09444040,
301 MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
302 MX6_MMDC_P0_MDCFG1, 0xFF328F64,
303 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
304 MX6_MMDC_P0_MDMISC, 0x00011740,
305 MX6_MMDC_P0_MDSCR, 0x00008000,
306 MX6_MMDC_P0_MDRWD, 0x000026D2,
307 MX6_MMDC_P0_MDOR, 0x00BE1023,
308 MX6_MMDC_P0_MDASP, 0x00000047,
309 MX6_MMDC_P0_MDCTL, 0x85190000,
310 MX6_MMDC_P0_MDSCR, 0x00888032,
311 MX6_MMDC_P0_MDSCR, 0x00008033,
312 MX6_MMDC_P0_MDSCR, 0x00008031,
313 MX6_MMDC_P0_MDSCR, 0x19408030,
314 MX6_MMDC_P0_MDSCR, 0x04008040,
315 MX6_MMDC_P0_MDREF, 0x00007800,
316 MX6_MMDC_P0_MPODTCTRL, 0x00000007,
317 MX6_MMDC_P0_MDPDC, 0x00025576,
318 MX6_MMDC_P0_MAPSR, 0x00011006,
319 MX6_MMDC_P0_MDSCR, 0x00000000,
320 /* enable AXI cache for VDOA/VPU/IPU */
322 MX6_IOMUXC_GPR4, 0xF00000CF,
323 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
324 MX6_IOMUXC_GPR6, 0x007F007F,
325 MX6_IOMUXC_GPR7, 0x007F007F,
328 static void ddr_init(int *table, int size)
332 for (i = 0; i < size / 2 ; i++)
333 writel(table[2 * i + 1], table[2 * i]);
336 static void spl_dram_init(void)
339 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
342 void board_init_f(ulong dummy)
344 /* DDR initialization */
347 /* setup AIPS and disable watchdog */
353 /* iomux and setup of uart and NAND pins */
354 board_early_init_f();
359 /* UART clocks enabled and gd valid - init serial console */
360 preloader_console_init();
363 memset(__bss_start, 0, __bss_end - __bss_start);
365 /* load/boot image from boot device */
366 board_init_r(NULL, 0);