board/liebherr/display5/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <spl.h>
   9 #include <linux/libfdt.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/mx6-ddr.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include "asm/arch/crm_regs.h"
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/imx-regs.h>
  17 #include "asm/arch/iomux.h"
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <environment.h>
  20 #include <fsl_esdhc.h>
  21 #include <netdev.h>
  22 #include "common.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  27         .dram_sdclk_0 = 0x00000030,
  28         .dram_sdclk_1 = 0x00000030,
  29         .dram_cas = 0x00000030,
  30         .dram_ras = 0x00000030,
  31         .dram_reset = 0x00000030,
  32         .dram_sdcke0 = 0x00003000,
  33         .dram_sdcke1 = 0x00003000,
  34         .dram_sdba2 = 0x00000000,
  35         .dram_sdodt0 = 0x00000030,
  36         .dram_sdodt1 = 0x00000030,
  37
  38         .dram_sdqs0 = 0x00000030,
  39         .dram_sdqs1 = 0x00000030,
  40         .dram_sdqs2 = 0x00000030,
  41         .dram_sdqs3 = 0x00000030,
  42         .dram_sdqs4 = 0x00000030,
  43         .dram_sdqs5 = 0x00000030,
  44         .dram_sdqs6 = 0x00000030,
  45         .dram_sdqs7 = 0x00000030,
  46
  47         .dram_dqm0 = 0x00000030,
  48         .dram_dqm1 = 0x00000030,
  49         .dram_dqm2 = 0x00000030,
  50         .dram_dqm3 = 0x00000030,
  51         .dram_dqm4 = 0x00000030,
  52         .dram_dqm5 = 0x00000030,
  53         .dram_dqm6 = 0x00000030,
  54         .dram_dqm7 = 0x00000030,
  55 };
  56
  57 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  58         .grp_ddr_type = 0x000c0000,
  59         .grp_ddrmode_ctl = 0x00020000,
  60         .grp_ddrpke = 0x00000000,
  61         .grp_addds = 0x00000030,
  62         .grp_ctlds = 0x00000030,
  63         .grp_ddrmode = 0x00020000,
  64         .grp_b0ds = 0x00000030,
  65         .grp_b1ds = 0x00000030,
  66         .grp_b2ds = 0x00000030,
  67         .grp_b3ds = 0x00000030,
  68         .grp_b4ds = 0x00000030,
  69         .grp_b5ds = 0x00000030,
  70         .grp_b6ds = 0x00000030,
  71         .grp_b7ds = 0x00000030,
  72 };
  73
  74 /* 4x128Mx16.cfg */
  75 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
  76         .p0_mpwldectrl0 = 0x002D0028,
  77         .p0_mpwldectrl1 = 0x0032002D,
  78         .p1_mpwldectrl0 = 0x00210036,
  79         .p1_mpwldectrl1 = 0x0019002E,
  80         .p0_mpdgctrl0 = 0x4349035C,
  81         .p0_mpdgctrl1 = 0x0348033D,
  82         .p1_mpdgctrl0 = 0x43550362,
  83         .p1_mpdgctrl1 = 0x03520316,
  84         .p0_mprddlctl = 0x41393940,
  85         .p1_mprddlctl = 0x3F3A3C47,
  86         .p0_mpwrdlctl = 0x413A423A,
  87         .p1_mpwrdlctl = 0x4042483E,
  88 };
  89
  90 /* MT41K128M16JT-125 (2Gb density) */
  91 static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  92         .mem_speed = 1600,
  93         .density = 2,
  94         .width = 16,
  95         .banks = 8,
  96         .rowaddr = 14,
  97         .coladdr = 10,
  98         .pagesz = 2,
  99         .trcd = 1375,
 100         .trcmin = 4875,
 101         .trasmin = 3500,
 102 };
 103
 104 static void ccgr_init(void)
 105 {
 106         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 107
 108         writel(0x00C03F3F, &ccm->CCGR0);
 109         writel(0x0030FC3F, &ccm->CCGR1);
 110         writel(0x0FFFCFC0, &ccm->CCGR2);
 111         writel(0x3FF00000, &ccm->CCGR3);
 112         writel(0x00FFF300, &ccm->CCGR4);
 113         writel(0x0F0000C3, &ccm->CCGR5);
 114         writel(0x000003FF, &ccm->CCGR6);
 115 }
 116
 117 static void spl_dram_init(void)
 118 {
 119         struct mx6_ddr_sysinfo sysinfo = {
 120                 /* width of data bus:0=16,1=32,2=64 */
 121                 .dsize = 2,
 122                 /* config for full 4GB range so that get_mem_size() works */
 123                 .cs_density = 32, /* 32Gb per CS */
 124                 /* single chip select */
 125                 .ncs = 1,
 126                 .cs1_mirror = 0,
 127                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 128                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 129                 .walat = 1,     /* Write additional latency */
 130                 .ralat = 5,     /* Read additional latency */
 131                 .mif3_mode = 3, /* Command prediction working mode */
 132                 .bi_on = 1,     /* Bank interleaving enabled */
 133                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 134                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 135                 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
 136                 .ddr_type = DDR_TYPE_DDR3,
 137                 .refsel = 1,    /* Refresh cycles at 32KHz */
 138                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 139         };
 140
 141         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 142         mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
 143 }
 144
 145 #ifdef CONFIG_SPL_SPI_SUPPORT
 146 static void displ5_init_ecspi(void)
 147 {
 148         displ5_set_iomux_ecspi_spl();
 149         enable_spi_clk(1, 1);
 150 }
 151 #else
 152 static inline void displ5_init_ecspi(void) { }
 153 #endif
 154
 155 #ifdef CONFIG_SPL_MMC_SUPPORT
 156 static struct fsl_esdhc_cfg usdhc_cfg = {
 157         .esdhc_base = USDHC4_BASE_ADDR,
 158         .max_bus_width = 8,
 159 };
 160
 161 int board_mmc_init(bd_t *bd)
 162 {
 163         displ5_set_iomux_usdhc_spl();
 164
 165         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 166         gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 167
 168         return fsl_esdhc_initialize(bd, &usdhc_cfg);
 169 }
 170 #endif
 171
 172 void board_init_f(ulong dummy)
 173 {
 174         ccgr_init();
 175
 176         arch_cpu_init();
 177
 178         gpr_init();
 179
 180         /* setup GP timer */
 181         timer_init();
 182
 183         displ5_set_iomux_uart_spl();
 184
 185         /* UART clocks enabled and gd valid - init serial console */
 186         preloader_console_init();
 187
 188         displ5_init_ecspi();
 189
 190         /* DDR initialization */
 191         spl_dram_init();
 192
 193         /* Clear the BSS. */
 194         memset(__bss_start, 0, __bss_end - __bss_start);
 195
 196         /* load/boot image from boot device */
 197         board_init_r(NULL, 0);
 198 }
 199
 200 void board_boot_order(u32 *spl_boot_list)
 201 {
 202         /* Default boot sequence SPI -> MMC */
 203         spl_boot_list[0] = spl_boot_device();
 204         spl_boot_list[1] = BOOT_DEVICE_MMC1;
 205         spl_boot_list[2] = BOOT_DEVICE_UART;
 206         spl_boot_list[3] = BOOT_DEVICE_NONE;
 207
 208 #ifdef CONFIG_SPL_ENV_SUPPORT
 209         /* 'fastboot' */
 210         const char *s;
 211
 212         env_init();
 213         env_load();
 214
 215         s = env_get("BOOT_FROM");
 216         if (s && strcmp(s, "ACTIVE") == 0) {
 217                 spl_boot_list[0] = BOOT_DEVICE_MMC1;
 218                 spl_boot_list[1] = spl_boot_device();
 219         }
 220 #endif
 221 }
 222
 223 void reset_cpu(ulong addr) {}
 224
 225 #ifdef CONFIG_SPL_LOAD_FIT
 226 int board_fit_config_name_match(const char *name)
 227 {
 228         return 0;
 229 }
 230 #endif
 231
 232 #ifdef CONFIG_SPL_OS_BOOT
 233 /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
 234 int spl_start_uboot(void)
 235 {
 236         /* break into full u-boot on 'c' */
 237         if (serial_tstc() && serial_getc() == 'c')
 238                 return 1;
 239
 240 #ifdef CONFIG_SPL_ENV_SUPPORT
 241         if (env_get_yesno("boot_os") != 1)
 242                 return 1;
 243 #endif
 244         return 0;
 245 }
 246 #endif