board/liebherr/display5/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <env.h>
  10 #include <image.h>
  11 #include <init.h>
  12 #include <serial.h>
  13 #include <spl.h>
  14 #include <linux/libfdt.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/mx6-ddr.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include "asm/arch/crm_regs.h"
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/arch/imx-regs.h>
  22 #include "asm/arch/iomux.h"
  23 #include <asm/mach-imx/iomux-v3.h>
  24 #include <asm/gpio.h>
  25 #include <fsl_esdhc_imx.h>
  26 #include <netdev.h>
  27 #include <bootcount.h>
  28 #include <watchdog.h>
  29 #include "common.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  34         .dram_sdclk_0 = 0x00000030,
  35         .dram_sdclk_1 = 0x00000030,
  36         .dram_cas = 0x00000030,
  37         .dram_ras = 0x00000030,
  38         .dram_reset = 0x00000030,
  39         .dram_sdcke0 = 0x00003000,
  40         .dram_sdcke1 = 0x00003000,
  41         .dram_sdba2 = 0x00000000,
  42         .dram_sdodt0 = 0x00000030,
  43         .dram_sdodt1 = 0x00000030,
  44
  45         .dram_sdqs0 = 0x00000030,
  46         .dram_sdqs1 = 0x00000030,
  47         .dram_sdqs2 = 0x00000030,
  48         .dram_sdqs3 = 0x00000030,
  49         .dram_sdqs4 = 0x00000030,
  50         .dram_sdqs5 = 0x00000030,
  51         .dram_sdqs6 = 0x00000030,
  52         .dram_sdqs7 = 0x00000030,
  53
  54         .dram_dqm0 = 0x00000030,
  55         .dram_dqm1 = 0x00000030,
  56         .dram_dqm2 = 0x00000030,
  57         .dram_dqm3 = 0x00000030,
  58         .dram_dqm4 = 0x00000030,
  59         .dram_dqm5 = 0x00000030,
  60         .dram_dqm6 = 0x00000030,
  61         .dram_dqm7 = 0x00000030,
  62 };
  63
  64 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  65         .grp_ddr_type = 0x000c0000,
  66         .grp_ddrmode_ctl = 0x00020000,
  67         .grp_ddrpke = 0x00000000,
  68         .grp_addds = 0x00000030,
  69         .grp_ctlds = 0x00000030,
  70         .grp_ddrmode = 0x00020000,
  71         .grp_b0ds = 0x00000030,
  72         .grp_b1ds = 0x00000030,
  73         .grp_b2ds = 0x00000030,
  74         .grp_b3ds = 0x00000030,
  75         .grp_b4ds = 0x00000030,
  76         .grp_b5ds = 0x00000030,
  77         .grp_b6ds = 0x00000030,
  78         .grp_b7ds = 0x00000030,
  79 };
  80
  81 /* 4x128Mx16.cfg */
  82 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
  83         .p0_mpwldectrl0 = 0x002D0028,
  84         .p0_mpwldectrl1 = 0x0032002D,
  85         .p1_mpwldectrl0 = 0x00210036,
  86         .p1_mpwldectrl1 = 0x0019002E,
  87         .p0_mpdgctrl0 = 0x4349035C,
  88         .p0_mpdgctrl1 = 0x0348033D,
  89         .p1_mpdgctrl0 = 0x43550362,
  90         .p1_mpdgctrl1 = 0x03520316,
  91         .p0_mprddlctl = 0x41393940,
  92         .p1_mprddlctl = 0x3F3A3C47,
  93         .p0_mpwrdlctl = 0x413A423A,
  94         .p1_mpwrdlctl = 0x4042483E,
  95 };
  96
  97 /* MT41K128M16JT-125 (2Gb density) */
  98 static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  99         .mem_speed = 1600,
 100         .density = 2,
 101         .width = 16,
 102         .banks = 8,
 103         .rowaddr = 14,
 104         .coladdr = 10,
 105         .pagesz = 2,
 106         .trcd = 1375,
 107         .trcmin = 4875,
 108         .trasmin = 3500,
 109 };
 110
 111 iomux_v3_cfg_t const uart_console_pads[] = {
 112         /* UART5 */
 113         MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 114         MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 115         MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 116         MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 117 };
 118
 119 void displ5_set_iomux_uart_spl(void)
 120 {
 121         SETUP_IOMUX_PADS(uart_console_pads);
 122 }
 123
 124 iomux_v3_cfg_t const misc_pads_spl[] = {
 125         /* Emergency recovery pin */
 126         MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 127 };
 128
 129 void displ5_set_iomux_misc_spl(void)
 130 {
 131         SETUP_IOMUX_PADS(misc_pads_spl);
 132 }
 133
 134 #ifdef CONFIG_MXC_SPI
 135 iomux_v3_cfg_t const ecspi2_pads[] = {
 136         /* SPI2, NOR Flash nWP, CS0 */
 137         MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 138         MX6_PAD_CSI0_DAT9__ECSPI2_MOSI  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 139         MX6_PAD_CSI0_DAT8__ECSPI2_SCLK  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 140         MX6_PAD_CSI0_DAT11__GPIO5_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
 141         MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL),
 142 };
 143
 144 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
 145 {
 146         if (bus != 1 || cs != 0)
 147                 return -EINVAL;
 148
 149         return IMX_GPIO_NR(5, 29);
 150 }
 151
 152 void displ5_set_iomux_ecspi_spl(void)
 153 {
 154         SETUP_IOMUX_PADS(ecspi2_pads);
 155 }
 156
 157 #else
 158 void displ5_set_iomux_ecspi_spl(void) {}
 159 #endif
 160
 161 #ifdef CONFIG_FSL_ESDHC_IMX
 162 iomux_v3_cfg_t const usdhc4_pads[] = {
 163         MX6_PAD_SD4_CLK__SD4_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD4_CMD__SD4_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_SD4_DAT0__SD4_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_SD4_DAT1__SD4_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_SD4_DAT2__SD4_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 168         MX6_PAD_SD4_DAT3__SD4_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 169         MX6_PAD_SD4_DAT4__SD4_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 170         MX6_PAD_SD4_DAT5__SD4_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 171         MX6_PAD_SD4_DAT6__SD4_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 172         MX6_PAD_SD4_DAT7__SD4_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 173         MX6_PAD_NANDF_ALE__SD4_RESET    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 174 };
 175
 176 void displ5_set_iomux_usdhc_spl(void)
 177 {
 178         SETUP_IOMUX_PADS(usdhc4_pads);
 179 }
 180
 181 #else
 182 void displ5_set_iomux_usdhc_spl(void) {}
 183 #endif
 184
 185 static void ccgr_init(void)
 186 {
 187         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 188
 189         writel(0x00C03F3F, &ccm->CCGR0);
 190         writel(0x0030FC3F, &ccm->CCGR1);
 191         writel(0x0FFFCFC0, &ccm->CCGR2);
 192         writel(0x3FF00000, &ccm->CCGR3);
 193         writel(0x00FFF300, &ccm->CCGR4);
 194         writel(0x0F0000C3, &ccm->CCGR5);
 195         writel(0x000003FF, &ccm->CCGR6);
 196 }
 197
 198 #ifdef CONFIG_MX6_DDRCAL
 199 static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
 200 {
 201         struct mx6_mmdc_calibration calibration = {0};
 202
 203         mmdc_read_calibration(sysinfo, &calibration);
 204
 205         debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
 206         debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
 207         debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
 208         debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
 209         debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
 210         debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
 211         debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
 212         debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
 213         debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
 214         debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
 215         debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
 216         debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
 217 }
 218
 219 static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
 220 {
 221         int ret;
 222
 223         /* Perform DDR DRAM calibration */
 224         udelay(100);
 225         ret = mmdc_do_write_level_calibration(sysinfo);
 226         if (ret) {
 227                 printf("DDR: Write level calibration error [%d]\n", ret);
 228                 return;
 229         }
 230
 231         ret = mmdc_do_dqs_calibration(sysinfo);
 232         if (ret) {
 233                 printf("DDR: DQS calibration error [%d]\n", ret);
 234                 return;
 235         }
 236
 237         spl_dram_print_cal(sysinfo);
 238 }
 239 #endif /* CONFIG_MX6_DDRCAL */
 240
 241 static void spl_dram_init(void)
 242 {
 243         struct mx6_ddr_sysinfo sysinfo = {
 244                 /* width of data bus:0=16,1=32,2=64 */
 245                 .dsize = 2,
 246                 /* config for full 4GB range so that get_mem_size() works */
 247                 .cs_density = 32, /* 32Gb per CS */
 248                 /* single chip select */
 249                 .ncs = 1,
 250                 .cs1_mirror = 0,
 251                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 252                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 253                 .walat = 1,     /* Write additional latency */
 254                 .ralat = 5,     /* Read additional latency */
 255                 .mif3_mode = 3, /* Command prediction working mode */
 256                 .bi_on = 1,     /* Bank interleaving enabled */
 257                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 258                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 259                 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
 260                 .ddr_type = DDR_TYPE_DDR3,
 261                 .refsel = 1,    /* Refresh cycles at 32KHz */
 262                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 263         };
 264
 265         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 266         mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
 267
 268 #ifdef CONFIG_MX6_DDRCAL
 269         spl_dram_perform_cal(&sysinfo);
 270 #endif
 271 }
 272
 273 #ifdef CONFIG_SPL_SPI_SUPPORT
 274 static void displ5_init_ecspi(void)
 275 {
 276         displ5_set_iomux_ecspi_spl();
 277         enable_spi_clk(1, 1);
 278 }
 279 #else
 280 static inline void displ5_init_ecspi(void) { }
 281 #endif
 282
 283 #ifdef CONFIG_SPL_MMC_SUPPORT
 284 static struct fsl_esdhc_cfg usdhc_cfg = {
 285         .esdhc_base = USDHC4_BASE_ADDR,
 286         .max_bus_width = 8,
 287 };
 288
 289 int board_mmc_init(bd_t *bd)
 290 {
 291         displ5_set_iomux_usdhc_spl();
 292
 293         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 294         gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 295
 296         return fsl_esdhc_initialize(bd, &usdhc_cfg);
 297 }
 298 #endif
 299
 300 void board_init_f(ulong dummy)
 301 {
 302         ccgr_init();
 303
 304         arch_cpu_init();
 305
 306         gpr_init();
 307
 308         /* setup GP timer */
 309         timer_init();
 310
 311         displ5_set_iomux_uart_spl();
 312
 313         /* UART clocks enabled and gd valid - init serial console */
 314         preloader_console_init();
 315
 316         displ5_init_ecspi();
 317
 318         /* DDR initialization */
 319         spl_dram_init();
 320
 321         /* Clear the BSS. */
 322         memset(__bss_start, 0, __bss_end - __bss_start);
 323
 324         displ5_set_iomux_misc_spl();
 325
 326         /* Initialize and reset WDT in SPL */
 327         hw_watchdog_init();
 328         WATCHDOG_RESET();
 329
 330         /* load/boot image from boot device */
 331         board_init_r(NULL, 0);
 332 }
 333
 334 #define EM_PAD IMX_GPIO_NR(3, 29)
 335 int board_check_emergency_pad(void)
 336 {
 337         int ret;
 338
 339         ret = gpio_direction_input(EM_PAD);
 340         if (ret)
 341                 return ret;
 342
 343         return !gpio_get_value(EM_PAD);
 344 }
 345
 346 void board_boot_order(u32 *spl_boot_list)
 347 {
 348         /* Default boot sequence SPI -> MMC */
 349         spl_boot_list[0] = spl_boot_device();
 350         spl_boot_list[1] = BOOT_DEVICE_MMC1;
 351         spl_boot_list[2] = BOOT_DEVICE_UART;
 352         spl_boot_list[3] = BOOT_DEVICE_NONE;
 353
 354         /*
 355          * In case of emergency PAD pressed, we always boot
 356          * to proper u-boot and perform recovery tasks there.
 357          */
 358         if (board_check_emergency_pad())
 359                 return;
 360
 361 #ifdef CONFIG_SPL_ENV_SUPPORT
 362         /* 'fastboot' */
 363         const char *s;
 364
 365         if (env_init() || env_load())
 366                 return;
 367
 368         s = env_get("BOOT_FROM");
 369         if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
 370                 spl_boot_list[0] = BOOT_DEVICE_MMC1;
 371                 spl_boot_list[1] = spl_boot_device();
 372         }
 373 #endif
 374 }
 375
 376 void reset_cpu(ulong addr) {}
 377
 378 #ifdef CONFIG_SPL_LOAD_FIT
 379 int board_fit_config_name_match(const char *name)
 380 {
 381         return 0;
 382 }
 383 #endif
 384
 385 #ifdef CONFIG_SPL_OS_BOOT
 386 /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
 387 int spl_start_uboot(void)
 388 {
 389         /* break into full u-boot on 'c' */
 390         if (serial_tstc() && serial_getc() == 'c')
 391                 return 1;
 392
 393 #ifdef CONFIG_SPL_ENV_SUPPORT
 394         if (env_get_yesno("boot_os") != 1)
 395                 return 1;
 396 #endif
 397         return 0;
 398 }
 399 #endif