board/kosagi/novena/video.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Novena video output support
   4  *
   5  * IT6251 code based on code Copyright (C) 2014 Sean Cross
   6  * from https://github.com/xobs/novena-linux.git commit
   7  * 3d85836ee1377d445531928361809612aa0a18db
   8  *
   9  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  10  */
  11
  12 #include <common.h>
  13 #include <linux/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/imx-regs.h>
  19 #include <asm/arch/iomux.h>
  20 #include <asm/arch/mxc_hdmi.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/mach-imx/iomux-v3.h>
  23 #include <asm/mach-imx/mxc_i2c.h>
  24 #include <asm/mach-imx/video.h>
  25 #include <i2c.h>
  26 #include <input.h>
  27 #include <ipu_pixfmt.h>
  28 #include <linux/fb.h>
  29 #include <linux/input.h>
  30 #include <malloc.h>
  31 #include <stdio_dev.h>
  32
  33 #include "novena.h"
  34
  35 #define IT6251_VENDOR_ID_LOW                            0x00
  36 #define IT6251_VENDOR_ID_HIGH                           0x01
  37 #define IT6251_DEVICE_ID_LOW                            0x02
  38 #define IT6251_DEVICE_ID_HIGH                           0x03
  39 #define IT6251_SYSTEM_STATUS                            0x0d
  40 #define IT6251_SYSTEM_STATUS_RINTSTATUS                 (1 << 0)
  41 #define IT6251_SYSTEM_STATUS_RHPDSTATUS                 (1 << 1)
  42 #define IT6251_SYSTEM_STATUS_RVIDEOSTABLE               (1 << 2)
  43 #define IT6251_SYSTEM_STATUS_RPLL_IOLOCK                (1 << 3)
  44 #define IT6251_SYSTEM_STATUS_RPLL_XPLOCK                (1 << 4)
  45 #define IT6251_SYSTEM_STATUS_RPLL_SPLOCK                (1 << 5)
  46 #define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK              (1 << 6)
  47 #define IT6251_REF_STATE                                0x0e
  48 #define IT6251_REF_STATE_MAIN_LINK_DISABLED             (1 << 0)
  49 #define IT6251_REF_STATE_AUX_CHANNEL_READ               (1 << 1)
  50 #define IT6251_REF_STATE_CR_PATTERN                     (1 << 2)
  51 #define IT6251_REF_STATE_EQ_PATTERN                     (1 << 3)
  52 #define IT6251_REF_STATE_NORMAL_OPERATION               (1 << 4)
  53 #define IT6251_REF_STATE_MUTED                          (1 << 5)
  54
  55 #define IT6251_REG_PCLK_CNT_LOW                         0x57
  56 #define IT6251_REG_PCLK_CNT_HIGH                        0x58
  57
  58 #define IT6521_RETRY_MAX                                20
  59
  60 static int it6251_is_stable(void)
  61 {
  62         const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
  63         const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
  64         int status;
  65         int clkcnt;
  66         int rpclkcnt;
  67         int refstate;
  68
  69         rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
  70                    ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
  71         debug("RPCLKCnt: %d\n", rpclkcnt);
  72
  73         status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
  74         debug("System status: 0x%02x\n", status);
  75
  76         clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
  77                  ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
  78                   0x0f00);
  79         debug("Clock: 0x%02x\n", clkcnt);
  80
  81         refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
  82         debug("Ref Link State: 0x%02x\n", refstate);
  83
  84         if ((refstate & 0x1f) != 0)
  85                 return 0;
  86
  87         /* If video is muted, that's a failure */
  88         if (refstate & IT6251_REF_STATE_MUTED)
  89                 return 0;
  90
  91         if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE))
  92                 return 0;
  93
  94         return 1;
  95 }
  96
  97 static int it6251_ready(void)
  98 {
  99         const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
 100
 101         /* Test if the IT6251 came out of reset by reading ID regs. */
 102         if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
 103                 return 0;
 104         if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
 105                 return 0;
 106         if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
 107                 return 0;
 108         if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
 109                 return 0;
 110
 111         return 1;
 112 }
 113
 114 static void it6251_program_regs(void)
 115 {
 116         const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
 117         const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
 118
 119         i2c_reg_write(caddr, 0x05, 0x00);
 120         mdelay(1);
 121
 122         /* set LVDSRX address, and enable */
 123         i2c_reg_write(caddr, 0xfd, 0xbc);
 124         i2c_reg_write(caddr, 0xfe, 0x01);
 125
 126         /*
 127          * LVDSRX
 128          */
 129         /* This write always fails, because the chip goes into reset */
 130         /* reset LVDSRX */
 131         i2c_reg_write(laddr, 0x05, 0xff);
 132         i2c_reg_write(laddr, 0x05, 0x00);
 133
 134         /* reset LVDSRX PLL */
 135         i2c_reg_write(laddr, 0x3b, 0x42);
 136         i2c_reg_write(laddr, 0x3b, 0x43);
 137
 138         /* something with SSC PLL */
 139         i2c_reg_write(laddr, 0x3c, 0x08);
 140         /* don't swap links, but writing reserved registers */
 141         i2c_reg_write(laddr, 0x0b, 0x88);
 142
 143         /* JEIDA, 8-bit depth  0x11, orig 0x42 */
 144         i2c_reg_write(laddr, 0x2c, 0x01);
 145         /* "reserved" */
 146         i2c_reg_write(laddr, 0x32, 0x04);
 147         /* "reserved" */
 148         i2c_reg_write(laddr, 0x35, 0xe0);
 149         /* "reserved" + clock delay */
 150         i2c_reg_write(laddr, 0x2b, 0x24);
 151
 152         /* reset LVDSRX pix clock */
 153         i2c_reg_write(laddr, 0x05, 0x02);
 154         i2c_reg_write(laddr, 0x05, 0x00);
 155
 156         /*
 157          * DPTX
 158          */
 159         /* set for two lane mode, normal op, no swapping, no downspread */
 160         i2c_reg_write(caddr, 0x16, 0x02);
 161
 162         /* some AUX channel EDID magic */
 163         i2c_reg_write(caddr, 0x23, 0x40);
 164
 165         /* power down lanes 3-0 */
 166         i2c_reg_write(caddr, 0x5c, 0xf3);
 167
 168         /* enable DP scrambling, change EQ CR phase */
 169         i2c_reg_write(caddr, 0x5f, 0x06);
 170
 171         /* color mode RGB, pclk/2 */
 172         i2c_reg_write(caddr, 0x60, 0x02);
 173         /* dual pixel input mode, no EO swap, no RGB swap */
 174         i2c_reg_write(caddr, 0x61, 0x04);
 175         /* M444B24 video format */
 176         i2c_reg_write(caddr, 0x62, 0x01);
 177
 178         /* vesa range / not interlace / vsync high / hsync high */
 179         i2c_reg_write(caddr, 0xa0, 0x0F);
 180
 181         /* hpd event timer set to 1.6-ish ms */
 182         i2c_reg_write(caddr, 0xc9, 0xf5);
 183
 184         /* more reserved magic */
 185         i2c_reg_write(caddr, 0xca, 0x4d);
 186         i2c_reg_write(caddr, 0xcb, 0x37);
 187
 188         /* enhanced framing mode, auto video fifo reset, video mute disable */
 189         i2c_reg_write(caddr, 0xd3, 0x03);
 190
 191         /* "vidstmp" and some reserved stuff */
 192         i2c_reg_write(caddr, 0xd4, 0x45);
 193
 194         /* queue number -- reserved */
 195         i2c_reg_write(caddr, 0xe7, 0xa0);
 196         /* info frame packets  and reserved */
 197         i2c_reg_write(caddr, 0xe8, 0x33);
 198         /* more AVI stuff */
 199         i2c_reg_write(caddr, 0xec, 0x00);
 200
 201         /* select PC master reg for aux channel? */
 202         i2c_reg_write(caddr, 0x23, 0x42);
 203
 204         /* send PC request commands */
 205         i2c_reg_write(caddr, 0x24, 0x00);
 206         i2c_reg_write(caddr, 0x25, 0x00);
 207         i2c_reg_write(caddr, 0x26, 0x00);
 208
 209         /* native aux read */
 210         i2c_reg_write(caddr, 0x2b, 0x00);
 211         /* back to internal */
 212         i2c_reg_write(caddr, 0x23, 0x40);
 213
 214         /* voltage swing level 3 */
 215         i2c_reg_write(caddr, 0x19, 0xff);
 216         /* pre-emphasis level 3 */
 217         i2c_reg_write(caddr, 0x1a, 0xff);
 218
 219         /* start link training */
 220         i2c_reg_write(caddr, 0x17, 0x01);
 221 }
 222
 223 static int it6251_init(void)
 224 {
 225         const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
 226         int reg;
 227         int tries, retries = 0;
 228
 229         for (retries = 0; retries < IT6521_RETRY_MAX; retries++) {
 230                 /* Program the chip. */
 231                 it6251_program_regs();
 232
 233                 /* Wait for video stable. */
 234                 for (tries = 0; tries < 100; tries++) {
 235                         reg = i2c_reg_read(caddr, 0x17);
 236                         /* Test Link CFG, STS, LCS read done. */
 237                         if ((reg & 0xe0) != 0xe0) {
 238                                 /* Not yet, wait a bit more. */
 239                                 mdelay(2);
 240                                 continue;
 241                         }
 242
 243                         /* Test if the video input is stable. */
 244                         if (it6251_is_stable())
 245                                 return 0;
 246                 }
 247                 /*
 248                  * If we couldn't stabilize, requeue and try again,
 249                  * because it means that the LVDS channel isn't
 250                  * stable yet.
 251                  */
 252                 printf("Display didn't stabilize.\n");
 253                 printf("This may be because the LVDS port is still in powersave mode.\n");
 254                 mdelay(50);
 255         }
 256
 257         return -EINVAL;
 258 }
 259
 260 static void enable_hdmi(struct display_info_t const *dev)
 261 {
 262         imx_enable_hdmi_phy();
 263 }
 264
 265 static int lvds_enabled;
 266
 267 static void enable_lvds(struct display_info_t const *dev)
 268 {
 269         if (lvds_enabled)
 270                 return;
 271
 272         /* ITE IT6251 power enable. */
 273         gpio_request(NOVENA_ITE6251_PWR_GPIO, "ite6251-power");
 274         gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
 275         mdelay(10);
 276         gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
 277         mdelay(20);
 278         lvds_enabled = 1;
 279 }
 280
 281 static int detect_lvds(struct display_info_t const *dev)
 282 {
 283         int ret, loops = 250;
 284
 285         enable_lvds(dev);
 286
 287         ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
 288         if (ret) {
 289                 puts("Cannot select IT6251 I2C bus.\n");
 290                 return 0;
 291         }
 292
 293         /* Wait up-to ~250 mS for the LVDS to come up. */
 294         while (--loops) {
 295                 ret = it6251_ready();
 296                 if (ret)
 297                         return ret;
 298
 299                 mdelay(1);
 300         }
 301
 302         return 0;
 303 }
 304
 305 struct display_info_t const displays[] = {
 306         {
 307                 /* HDMI Output */
 308                 .bus    = -1,
 309                 .addr   = 0,
 310                 .pixfmt = IPU_PIX_FMT_RGB24,
 311                 .detect = detect_hdmi,
 312                 .enable = enable_hdmi,
 313                 .mode   = {
 314                         .name           = "HDMI",
 315                         .refresh        = 60,
 316                         .xres           = 1024,
 317                         .yres           = 768,
 318                         .pixclock       = 15384,
 319                         .left_margin    = 220,
 320                         .right_margin   = 40,
 321                         .upper_margin   = 21,
 322                         .lower_margin   = 7,
 323                         .hsync_len      = 60,
 324                         .vsync_len      = 10,
 325                         .sync           = FB_SYNC_EXT,
 326                         .vmode          = FB_VMODE_NONINTERLACED
 327                 },
 328         }, {
 329                 /* LVDS Output: N133HSE-EA1 Rev. C1 */
 330                 .bus    = -1,
 331                 .pixfmt = IPU_PIX_FMT_RGB24,
 332                 .detect = detect_lvds,
 333                 .enable = enable_lvds,
 334                 .mode   = {
 335                         .name           = "Chimei-FHD",
 336                         .refresh        = 60,
 337                         .xres           = 1920,
 338                         .yres           = 1080,
 339                         .pixclock       = 15384,
 340                         .left_margin    = 148,
 341                         .right_margin   = 88,
 342                         .upper_margin   = 36,
 343                         .lower_margin   = 4,
 344                         .hsync_len      = 44,
 345                         .vsync_len      = 5,
 346                         .sync           = FB_SYNC_HOR_HIGH_ACT |
 347                                           FB_SYNC_VERT_HIGH_ACT |
 348                                           FB_SYNC_EXT,
 349                         .vmode          = FB_VMODE_NONINTERLACED,
 350                 },
 351         },
 352 };
 353
 354 size_t display_count = ARRAY_SIZE(displays);
 355
 356 static void enable_vpll(void)
 357 {
 358         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 359         int timeout = 100000;
 360
 361         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 362
 363         clrsetbits_le32(&ccm->analog_pll_video,
 364                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 365                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 366                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 367                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 368
 369         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 370         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 371
 372         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 373
 374         while (timeout--)
 375                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 376                         break;
 377         if (timeout < 0)
 378                 printf("Warning: video pll lock timeout!\n");
 379
 380         clrsetbits_le32(&ccm->analog_pll_video,
 381                         BM_ANADIG_PLL_VIDEO_BYPASS,
 382                         BM_ANADIG_PLL_VIDEO_ENABLE);
 383 }
 384
 385 void setup_display_clock(void)
 386 {
 387         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 388         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 389
 390         enable_ipu_clock();
 391         enable_vpll();
 392         imx_setup_hdmi();
 393
 394         /* Turn on IPU LDB DI0 clocks */
 395         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 396
 397         /* Switch LDB DI0 to PLL5 (Video PLL) */
 398         clrsetbits_le32(&mxc_ccm->cs2cdr,
 399                         MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
 400                         (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
 401
 402         /* LDB clock div by 3.5 */
 403         clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 404
 405         /* DI0 clock derived from ldb_di0_clk */
 406         clrsetbits_le32(&mxc_ccm->chsccdr,
 407                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 408                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 409                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
 410                         );
 411
 412         /* Enable both LVDS channels, both connected to DI0. */
 413         writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
 414                IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
 415                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 416                IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
 417                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 418                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 419                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
 420                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 421                &iomux->gpr[2]);
 422
 423         clrsetbits_le32(&iomux->gpr[3],
 424                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 425                         IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
 426                         (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 427                          IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
 428                         (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 429                          IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
 430                         );
 431 }
 432
 433 void setup_display_lvds(void)
 434 {
 435         int ret;
 436
 437         ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
 438         if (ret) {
 439                 puts("Cannot select LVDS-to-eDP I2C bus.\n");
 440                 return;
 441         }
 442
 443         /* The IT6251 should be ready now, if it's not, it's not connected. */
 444         ret = it6251_ready();
 445         if (!ret)
 446                 return;
 447
 448         /* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
 449         ret = it6251_init();
 450         if (!ret) {
 451                 gpio_request(NOVENA_BACKLIGHT_PWR_GPIO, "backlight-power");
 452                 gpio_request(NOVENA_BACKLIGHT_PWM_GPIO, "backlight-pwm");
 453                 /* Backlight power enable. */
 454                 gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
 455                 /* PWM backlight pin, always on for full brightness. */
 456                 gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1);
 457         }
 458 }