2 * (C) Copyright 2007-2008
3 * Larry Johnson, lrj@acm.org
5 * (C) Copyright 2006-2008
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
10 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/processor.h>
34 #include <asm/bitops.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
40 ulong flash_get_size(ulong base, int banknum);
42 int board_early_init_f(void)
44 u32 sdr0_pfc1, sdr0_pfc2;
48 mtdcr(ebccfga, xbcfg);
49 mtdcr(ebccfgd, 0xb8400000);
52 * Setup the interrupt controller polarities, triggers, etc.
54 mtdcr(uic0sr, 0xffffffff); /* clear all */
55 mtdcr(uic0er, 0x00000000); /* disable all */
56 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
57 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
58 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
59 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
60 mtdcr(uic0sr, 0xffffffff); /* clear all */
62 mtdcr(uic1sr, 0xffffffff); /* clear all */
63 mtdcr(uic1er, 0x00000000); /* disable all */
64 mtdcr(uic1cr, 0x00000000); /* all non-critical */
65 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
66 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
67 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
68 mtdcr(uic1sr, 0xffffffff); /* clear all */
70 mtdcr(uic2sr, 0xffffffff); /* clear all */
71 mtdcr(uic2er, 0x00000000); /* disable all */
72 mtdcr(uic2cr, 0x00000000); /* all non-critical */
73 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
74 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
75 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
76 mtdcr(uic2sr, 0xffffffff); /* clear all */
78 /* take sim card reader and CF controller out of reset */
79 out_8((u8 *) CFG_CPLD_BASE + 0x04, 0x80);
81 /* Configure the two Ethernet PHYs. For each PHY, configure for fiber
82 * if the SFP module is present, and for copper if it is not present.
84 for (eth = 0; eth < 2; ++eth) {
85 if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) {
86 /* SFP module not present: configure PHY for copper. */
87 /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
88 out_8((u8 *) CFG_CPLD_BASE + 0x06,
89 in_8((u8 *) CFG_CPLD_BASE + 0x06) |
92 /* SFP module present: configure PHY for fiber and
94 gpio_write_bit(CFG_GPIO_PHY0_FIBER_SEL + eth, 1);
95 gpio_write_bit(CFG_GPIO_SFP0_TX_EN_ + eth, 0);
98 /* enable Ethernet: set GPIO45 and GPIO46 to 1 */
99 gpio_write_bit(CFG_GPIO_PHY0_EN, 1);
100 gpio_write_bit(CFG_GPIO_PHY1_EN, 1);
102 /* select Ethernet pins */
103 mfsdr(SDR0_PFC1, sdr0_pfc1);
104 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
105 SDR0_PFC1_SELECT_CONFIG_4;
106 mfsdr(SDR0_PFC2, sdr0_pfc2);
107 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
108 SDR0_PFC2_SELECT_CONFIG_4;
109 mtsdr(SDR0_PFC2, sdr0_pfc2);
110 mtsdr(SDR0_PFC1, sdr0_pfc1);
112 /* PCI arbiter enabled */
113 mfsdr(sdr_pci0, reg);
114 mtsdr(sdr_pci0, 0x80000000 | reg);
119 static int man_data_read(unsigned int addr)
122 * Read an octet of data from address "addr" in the manufacturer's
123 * information serial EEPROM, or -1 on error.
127 if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
128 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
129 debug("man_data_read(0x%02X) failed\n", addr);
132 debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
136 static unsigned int man_data_field_addr(unsigned int const field)
139 * The manufacturer's information serial EEPROM contains a sequence of
140 * zero-delimited fields. Return the starting address of field "field",
145 if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
146 /* Only format "A" is currently supported */
149 for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
150 if ('\0' == man_data_read(addr))
153 return (addr < 256) ? addr : 0;
156 static char *man_data_read_field(char s[], unsigned const field,
157 unsigned const length)
160 * Place the null-terminated contents of field "field" of length
161 * "length" from the manufacturer's information serial EEPROM into
162 * string "s[length + 1]" and return a pointer to s, or return 0 on
163 * error. In either case the original contents of s[] is not preserved.
167 addr = man_data_field_addr(field);
168 if (0 == addr || addr + length >= 255)
171 for (i = 0; i < length; ++i) {
172 int const c = man_data_read(addr++);
179 if (0 != man_data_read(addr))
186 static void set_serial_number(void)
189 * If the environmental variable "serial#" is not set, try to set it
190 * from the manufacturer's information serial EEPROM.
192 char s[MAN_SERIAL_NO_LENGTH + 1];
194 if (0 == getenv("serial#") &&
195 0 != man_data_read_field(s, MAN_SERIAL_NO_FIELD,
196 MAN_SERIAL_NO_LENGTH))
197 setenv("serial#", s);
200 static void set_mac_addresses(void)
203 * If the environmental variables "ethaddr" and/or "eth1addr" are not
204 * set, try to set them from the manufacturer's information serial
207 char s[MAN_MAC_ADDR_LENGTH + 1];
209 if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
212 if (0 == man_data_read_field(s, MAN_MAC_ADDR_FIELD,
213 MAN_MAC_ADDR_LENGTH))
216 if (0 == getenv("ethaddr"))
217 setenv("ethaddr", s);
219 if (0 == getenv("eth1addr")) {
220 ++s[MAN_MAC_ADDR_LENGTH - 1];
221 setenv("eth1addr", s);
225 int misc_init_r(void)
230 unsigned long usb2d0cr = 0;
231 unsigned long usb2phy0cr, usb2h0cr = 0;
232 unsigned long sdr0_pfc1;
233 char *act = getenv("usbact");
235 /* Re-do flash sizing to get full correct info */
237 /* adjust flash start and offset */
238 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
239 gd->bd->bi_flashoffset = 0;
241 mtdcr(ebccfga, pb0cr);
242 pbcr = mfdcr(ebccfgd);
243 size_val = ffs(gd->bd->bi_flashsize) - 21;
244 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
245 mtdcr(ebccfga, pb0cr);
246 mtdcr(ebccfgd, pbcr);
249 * Re-check to get correct base address
251 flash_get_size(gd->bd->bi_flashstart, 0);
253 /* Monitor protection ON by default */
254 (void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff,
257 /* Env protection ON by default */
258 (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
259 CFG_ENV_ADDR_REDUND + 2 * CFG_ENV_SECT_SIZE - 1,
265 if (act == NULL || strcmp(act, "hostdev") == 0) {
267 mfsdr(SDR0_PFC1, sdr0_pfc1);
268 mfsdr(SDR0_USB2D0CR, usb2d0cr);
269 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
270 mfsdr(SDR0_USB2H0CR, usb2h0cr);
272 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
273 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
274 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
275 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
276 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
277 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
278 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
279 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
280 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
281 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
284 * An 8-bit/60MHz interface is the only possible alternative
285 * when connecting the Device to the PHY
287 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
288 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
291 * To enable the USB 2.0 Device function
292 * through the UTMI interface
294 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
295 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
297 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
298 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
300 mtsdr(SDR0_PFC1, sdr0_pfc1);
301 mtsdr(SDR0_USB2D0CR, usb2d0cr);
302 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
303 mtsdr(SDR0_USB2H0CR, usb2h0cr);
307 mtsdr(SDR0_SRST1, 0x00000000);
309 mtsdr(SDR0_SRST0, 0x00000000);
311 printf("USB: Host(int phy) Device(ext phy)\n");
313 } else if (strcmp(act, "dev") == 0) {
314 /*-------------------PATCH-------------------------------*/
315 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
317 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
318 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
319 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
320 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
321 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
322 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
323 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
324 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
325 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
328 mtsdr(SDR0_SRST1, 0x672c6000);
331 mtsdr(SDR0_SRST0, 0x00000080);
334 mtsdr(SDR0_SRST1, 0x60206000);
336 *(unsigned int *)(0xe0000350) = 0x00000001;
339 mtsdr(SDR0_SRST1, 0x60306000);
340 /*-------------------PATCH-------------------------------*/
343 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
344 mfsdr(SDR0_USB2H0CR, usb2h0cr);
345 mfsdr(SDR0_USB2D0CR, usb2d0cr);
346 mfsdr(SDR0_PFC1, sdr0_pfc1);
348 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
349 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
350 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
351 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
352 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
353 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
354 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
355 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
356 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
357 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
359 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
360 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
362 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
363 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
365 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
366 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
368 mtsdr(SDR0_USB2H0CR, usb2h0cr);
369 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
370 mtsdr(SDR0_USB2D0CR, usb2d0cr);
371 mtsdr(SDR0_PFC1, sdr0_pfc1);
375 mtsdr(SDR0_SRST1, 0x00000000);
377 mtsdr(SDR0_SRST0, 0x00000000);
379 printf("USB: Device(int phy)\n");
382 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
383 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
384 mtsdr(SDR0_SRST1, reg);
387 * Clear PLB4A0_ACR[WRP]
388 * This fix will make the MAL burst disabling patch for the Linux
389 * EMAC driver obsolete.
391 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
392 mtdcr(plb4_acr, reg);
401 char const *const s = getenv("serial#");
402 u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0);
404 printf("Board: Korat, Rev. %X", rev);
406 printf(", serial# %s", s);
408 printf(", Ethernet PHY 0: ");
409 if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL))
415 if (gpio_read_out_bit(CFG_GPIO_PHY1_FIBER_SEL))
424 #if defined(CFG_DRAM_TEST)
427 unsigned long *mem = (unsigned long *)0;
428 const unsigned long kend = (1024 / sizeof(unsigned long));
433 /* TODO: find correct size of SDRAM */
434 for (k = 0; k < CFG_MBYTES_SDRAM;
435 ++k, mem += (1024 / sizeof(unsigned long))) {
437 printf("%3d MB\r", k / 1024);
439 memset(mem, 0xaaaaaaaa, 1024);
440 for (n = 0; n < kend; ++n) {
441 if (mem[n] != 0xaaaaaaaa) {
442 printf("SDRAM test fails at: %08x\n",
448 memset(mem, 0x55555555, 1024);
449 for (n = 0; n < kend; ++n) {
450 if (mem[n] != 0x55555555) {
451 printf("SDRAM test fails at: %08x\n",
457 printf("SDRAM test passes\n");
460 #endif /* defined(CFG_DRAM_TEST) */
465 * This routine is called just prior to registering the hose and gives
466 * the board the opportunity to check things. Returning a value of zero
467 * indicates that things are bad & PCI initialization should be aborted.
469 * Different boards may wish to customize the pci controller structure
470 * (add regions, override default access routines, etc) or perform
471 * certain pre-initialization actions.
473 #if defined(CONFIG_PCI)
474 int pci_pre_init(struct pci_controller *hose)
479 * Set priority for all PLB3 devices to 0.
480 * Set PLB3 arbiter to fair mode.
482 mfsdr(sdr_amp1, addr);
483 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
484 addr = mfdcr(plb3_acr);
485 mtdcr(plb3_acr, addr | 0x80000000);
488 * Set priority for all PLB4 devices to 0.
490 mfsdr(sdr_amp0, addr);
491 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
492 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
493 mtdcr(plb4_acr, addr);
496 * Set Nebula PLB4 arbiter to fair mode.
499 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
500 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
501 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
502 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
503 mtdcr(plb0_acr, addr);
506 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
507 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
508 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
509 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
510 mtdcr(plb1_acr, addr);
514 #endif /* defined(CONFIG_PCI) */
519 * The bootstrap configuration provides default settings for the pci
520 * inbound map (PIM). But the bootstrap config choices are limited and
521 * may not be sufficient for a given board.
523 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
524 void pci_target_init(struct pci_controller *hose)
527 * Set up Direct MMIO registers
530 * PowerPC440EPX PCI Master configuration.
531 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
532 * PLB address 0xA0000000-0xDFFFFFFF
533 * ==> PCI address 0xA0000000-0xDFFFFFFF
534 * Use byte reversed out routines to handle endianess.
535 * Make this region non-prefetchable.
537 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
538 /* - disabled b4 setting */
539 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
540 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
541 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
542 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
543 /* and enable region */
545 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
546 /* - disabled b4 setting */
547 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
548 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
549 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
550 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
551 /* and enable region */
553 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
554 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
555 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
556 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
559 * Set up Configuration registers
562 /* Program the board's subsystem id/vendor id */
563 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
564 CFG_PCI_SUBSYS_VENDORID);
565 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
567 /* Configure command register as bus master */
568 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
570 /* 240nS PCI clock */
571 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
573 /* No error reporting */
574 pci_write_config_word(0, PCI_ERREN, 0);
576 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
579 * Set up Configuration registers for on-board NEC uPD720101 USB
582 pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
584 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
586 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
587 void pci_master_init(struct pci_controller *hose)
589 unsigned short temp_short;
592 * Write the PowerPC440 EP PCI Configuration regs.
593 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
594 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
596 pci_read_config_word(0, PCI_COMMAND, &temp_short);
597 pci_write_config_word(0, PCI_COMMAND,
598 temp_short | PCI_COMMAND_MASTER |
606 * This routine is called to determine if a pci scan should be
607 * performed. With various hardware environments (especially cPCI and
608 * PPMC) it's insufficient to depend on the state of the arbiter enable
609 * bit in the strap register, or generic host/adapter assumptions.
611 * Rather than hard-code a bad assumption in the general 440 code, the
612 * 440 pci code requires the board to decide at runtime.
614 * Return 0 for adapter mode, non-zero for host (monarch) mode.
616 #if defined(CONFIG_PCI)
617 int is_pci_host(struct pci_controller *hose)
619 /* Korat is always configured as host. */
622 #endif /* defined(CONFIG_PCI) */
624 #if defined(CONFIG_POST)
626 * Returns 1 if keys pressed to start the power-on long-running tests
627 * Called from board_init_f().
629 int post_hotkeys_pressed(void)
631 return 0; /* No hotkeys supported */
633 #endif /* CONFIG_POST */