1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 Kontron Electronics GmbH
6 #include <asm/arch/imx8mm_pins.h>
7 #include <asm/arch/clock.h>
8 #include <asm/arch/ddr.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/global_data.h>
13 #include <asm/mach-imx/boot_mode.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <dm/uclass.h>
16 #include <dm/device.h>
17 #include <dm/uclass-internal.h>
18 #include <dm/device-internal.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <power/pca9450.h>
25 #include <power/pmic.h>
28 DECLARE_GLOBAL_DATA_PTR;
32 BOARD_TYPE_KTN_N801X_LVDS,
36 #define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
37 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
38 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
39 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
41 #define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23)
43 static iomux_v3_cfg_t const i2c1_pads[] = {
44 IMX8MM_PAD_I2C1_SCL_I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
45 IMX8MM_PAD_I2C1_SDA_I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
48 static iomux_v3_cfg_t const i2c2_pads[] = {
49 IMX8MM_PAD_I2C2_SCL_I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
50 IMX8MM_PAD_I2C2_SDA_I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
53 static iomux_v3_cfg_t const touch_gpio[] = {
54 IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
57 static iomux_v3_cfg_t const uart_pads[] = {
58 IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
59 IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
62 static iomux_v3_cfg_t const wdog_pads[] = {
63 IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
66 int spl_board_boot_device(enum boot_device boot_dev_spl)
68 switch (boot_dev_spl) {
70 return BOOT_DEVICE_BOARD;
72 return BOOT_DEVICE_SPI;
75 return BOOT_DEVICE_MMC1;
78 return BOOT_DEVICE_MMC2;
80 return BOOT_DEVICE_NONE;
84 bool check_ram_available(long size)
86 long sz = get_ram_size((long *)PHYS_SDRAM, size);
94 static void spl_dram_init(void)
99 * Try the default DDR settings in lpddr4_timing.c to
100 * comply with the Micron 4GB DDR.
102 if (!ddr_init(&dram_timing) && check_ram_available(SZ_4G)) {
106 * Overwrite some values to comply with the Micron 1GB/2GB DDRs.
108 dram_timing.ddrc_cfg[2].val = 0xa1080020;
109 dram_timing.ddrc_cfg[37].val = 0x1f;
111 dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x110;
112 dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x1;
113 dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x110;
114 dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1;
115 dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110;
116 dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1;
117 dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x110;
118 dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x1;
120 if (!ddr_init(&dram_timing)) {
121 if (check_ram_available(SZ_2G))
123 else if (check_ram_available(SZ_1G))
129 printf("Failed to initialize DDR RAM!\n");
133 printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n", size);
134 writel(size, M4_BOOTROM_BASE_ADDR);
137 static void touch_reset(void)
140 * Toggle the reset of the touch panel.
142 imx_iomux_v3_setup_multiple_pads(touch_gpio, ARRAY_SIZE(touch_gpio));
144 gpio_request(TOUCH_RESET_GPIO, "touch_reset");
145 gpio_direction_output(TOUCH_RESET_GPIO, 0);
147 gpio_direction_output(TOUCH_RESET_GPIO, 1);
151 static int i2c_detect(u8 bus, u16 addr)
153 struct udevice *udev;
157 * Try to probe the touch controller to check if an LVDS panel is
160 ret = i2c_get_chip_for_busnum(bus, addr, 0, &udev);
167 int do_board_detect(void)
172 * Check the I2C touch controller to detect a LVDS panel.
174 imx_iomux_v3_setup_multiple_pads(i2c2_pads, ARRAY_SIZE(i2c2_pads));
177 if (i2c_detect(1, 0x5d) == 0) {
178 printf("Touch controller detected, assuming LVDS panel...\n");
183 * Check the I2C PMIC to detect the deprecated SoM with DA9063.
185 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
187 if (i2c_detect(0, 0x58) == 0) {
188 printf("### ATTENTION: DEPRECATED SOM REVISION (N8010 Rev0) DETECTED! ###\n");
189 printf("### THIS HW IS NOT SUPPRTED AND BOOTING WILL PROBABLY FAIL ###\n");
190 printf("### PLEASE UPGRADE TO LATEST MODULE ###\n");
194 gd->board_type = BOARD_TYPE_KTN_N801X_LVDS;
196 gd->board_type = BOARD_TYPE_KTN_N801X;
201 int board_fit_config_name_match(const char *name)
203 if (gd->board_type == BOARD_TYPE_KTN_N801X_LVDS && is_imx8mm() &&
204 !strncmp(name, "imx8mm-kontron-n801x-s-lvds", 27))
207 if (gd->board_type == BOARD_TYPE_KTN_N801X && is_imx8mm() &&
208 !strncmp(name, "imx8mm-kontron-n801x-s", 22))
214 void spl_board_init(void)
219 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
220 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
222 printf("Failed to initialize %s: %d\n", dev->name, ret);
225 puts("Normal Boot\n");
227 ret = uclass_get_device_by_name(UCLASS_CLK,
228 "clock-controller@30380000",
231 printf("Failed to find clock node. Check device tree\n");
234 int board_early_init_f(void)
236 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
238 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
240 set_wdog_reset(wdog);
242 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
247 static int power_init_board(void)
250 int ret = pmic_get("pmic@25", &dev);
253 puts("No pmic found\n");
258 /* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
259 pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
261 /* increase VDD_DRAM to 0.95V for 1.5GHz DDR */
262 pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
264 /* set VDD_SNVS_0V8 from default 0.85V to 0.8V */
265 pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
267 /* set WDOG_B_CFG to cold reset */
268 pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
273 void board_init_f(ulong dummy)
281 board_early_init_f();
285 preloader_console_init();
288 memset(__bss_start, 0, __bss_end - __bss_start);
292 debug("spl_init() failed: %d\n", ret);
298 /* PMIC initialization */
301 /* DDR initialization */
304 /* Detect the board type */
307 board_init_r(NULL, 0);
310 void board_boot_order(u32 *spl_boot_list)
312 u32 bootdev = spl_boot_device();
315 * The default boot fuse settings use the SD card (MMC2) as primary
316 * boot device, but allow SPI NOR as a fallback boot device.
317 * We can't detect the fallback case and spl_boot_device() will return
318 * BOOT_DEVICE_MMC2 despite the actual boot device being SPI NOR.
319 * Therefore we try to load U-Boot proper vom SPI NOR after loading
320 * from MMC has failed.
322 spl_boot_list[0] = bootdev;
325 case BOOT_DEVICE_MMC1:
326 case BOOT_DEVICE_MMC2:
327 spl_boot_list[1] = BOOT_DEVICE_SPI;