1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Kontron Electronics GmbH
6 #include <asm/arch/clock.h>
7 #include <asm/arch/crm_regs.h>
8 #include <asm/arch/mx6-pins.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/global_data.h>
13 #include <asm/mach-imx/iomux-v3.h>
14 #include <fsl_esdhc_imx.h>
16 #include <linux/delay.h>
17 #include <linux/sizes.h>
18 #include <linux/errno.h>
20 #include <sl-mx6ul-common.h>
22 DECLARE_GLOBAL_DATA_PTR;
25 BOARD_TYPE_KTN_SL_UL = 1,
26 BOARD_TYPE_KTN_SL_ULL,
30 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
32 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
34 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
36 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define USDHC_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
43 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
46 #include <asm/arch/mx6-ddr.h>
48 static iomux_v3_cfg_t const usdhc1_pads[] = {
49 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
50 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
51 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
52 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
53 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
54 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
60 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
62 static iomux_v3_cfg_t const usdhc2_pads[] = {
63 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
64 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
65 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
66 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
67 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
68 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
70 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
73 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
75 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
76 {USDHC1_BASE_ADDR, 0, 4},
77 {USDHC2_BASE_ADDR, 0, 4},
80 int board_mmc_getcd(struct mmc *mmc)
82 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
85 switch (cfg->esdhc_base) {
86 case USDHC1_BASE_ADDR:
87 ret = !gpio_get_value(USDHC1_CD_GPIO);
89 case USDHC2_BASE_ADDR:
90 // This SDHC interface does not use a CD pin
98 int board_mmc_init(struct bd_info *bis)
103 * According to the board_mmc_init() the following map is done:
104 * (U-boot device node) (Physical Port)
108 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
111 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
112 gpio_direction_input(USDHC1_CD_GPIO);
113 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
116 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
117 gpio_direction_output(USDHC2_PWR_GPIO, 0);
119 gpio_direction_output(USDHC2_PWR_GPIO, 1);
120 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
123 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n",
128 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
130 printf("Warning: failed to initialize mmc dev %d\n", i);
137 iomux_v3_cfg_t const ecspi2_pads[] = {
138 MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
139 MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
140 MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
141 MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
144 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
146 return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
147 ? (IMX_GPIO_NR(4, 22)) : -1;
150 static void setup_spi(void)
152 gpio_request(IMX_GPIO_NR(4, 22), "spi2_cs0");
153 gpio_direction_output(IMX_GPIO_NR(4, 22), 1);
154 imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
156 enable_spi_clk(true, 1);
159 static iomux_v3_cfg_t const uart4_pads[] = {
160 MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
161 MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
164 static void setup_iomux_uart(void)
166 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
169 // DDR 256MB (Hynix H5TQ2G63DFR)
170 static struct mx6_ddr3_cfg mem_256M_ddr = {
183 static struct mx6_mmdc_calibration mx6_mmcd_256M_calib = {
184 .p0_mpwldectrl0 = 0x00000000,
185 .p0_mpdgctrl0 = 0x01340134,
186 .p0_mprddlctl = 0x40405052,
187 .p0_mpwrdlctl = 0x40404E48,
190 // DDR 512MB (Hynix H5TQ4G63DFR)
191 static struct mx6_ddr3_cfg mem_512M_ddr = {
204 static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = {
205 .p0_mpwldectrl0 = 0x00000000,
206 .p0_mpdgctrl0 = 0X01440144,
207 .p0_mprddlctl = 0x40405454,
208 .p0_mpwrdlctl = 0x40404E4C,
211 // Common DDR parameters (256MB and 512MB)
212 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
213 .grp_addds = 0x00000028,
214 .grp_ddrmode_ctl = 0x00020000,
215 .grp_b0ds = 0x00000028,
216 .grp_ctlds = 0x00000028,
217 .grp_b1ds = 0x00000028,
218 .grp_ddrpke = 0x00000000,
219 .grp_ddrmode = 0x00020000,
220 .grp_ddr_type = 0x000c0000,
223 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
224 .dram_dqm0 = 0x00000028,
225 .dram_dqm1 = 0x00000028,
226 .dram_ras = 0x00000028,
227 .dram_cas = 0x00000028,
228 .dram_odt0 = 0x00000028,
229 .dram_odt1 = 0x00000028,
230 .dram_sdba2 = 0x00000000,
231 .dram_sdclk_0 = 0x00000028,
232 .dram_sdqs0 = 0x00000028,
233 .dram_sdqs1 = 0x00000028,
234 .dram_reset = 0x00000028,
237 struct mx6_ddr_sysinfo ddr_sysinfo = {
243 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
244 .walat = 1, /* Write additional latency */
245 .ralat = 5, /* Read additional latency */
246 .mif3_mode = 3, /* Command prediction working mode */
247 .bi_on = 1, /* Bank interleaving enabled */
248 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
249 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
250 .ddr_type = DDR_TYPE_DDR3,
251 .refsel = 0, /* Refresh cycles at 64KHz */
252 .refr = 1, /* 2 refresh commands per refresh cycle */
255 static void ccgr_init(void)
257 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
259 writel(0xFFFFFFFF, &ccm->CCGR0);
260 writel(0xFFFFFFFF, &ccm->CCGR1);
261 writel(0xFFFFFFFF, &ccm->CCGR2);
262 writel(0xFFFFFFFF, &ccm->CCGR3);
263 writel(0xFFFFFFFF, &ccm->CCGR4);
264 writel(0xFFFFFFFF, &ccm->CCGR5);
265 writel(0xFFFFFFFF, &ccm->CCGR6);
266 writel(0xFFFFFFFF, &ccm->CCGR7);
269 static void spl_dram_init(void)
273 // DDR RAM connection is always 16 bit wide. Init IOs.
274 mx6ul_dram_iocfg(16, &mx6_ddr_ioregs, &mx6_grp_ioregs);
276 // Try to detect the 512MB RAM chip first.
277 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_512M_calib, &mem_512M_ddr);
279 // Get the available RAM size
280 size = get_ram_size((void *)PHYS_SDRAM, SZ_512M);
284 if (size == SZ_512M) {
285 // 512MB RAM was detected
287 } else if (size == SZ_256M) {
288 // 256MB RAM was detected, use correct config and calibration
289 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_256M_calib, &mem_256M_ddr);
291 printf("Invalid DDR RAM size detected: %x\n", size);
295 static int do_board_detect(void)
298 gd->board_type = BOARD_TYPE_KTN_SL_UL;
299 else if (is_mx6ull())
300 gd->board_type = BOARD_TYPE_KTN_SL_ULL;
302 printf("Kontron SL i.MX6UL%s (N6%s1x) module, %lu MB RAM detected\n",
303 is_mx6ull() ? "L" : "", is_mx6ull() ? "4" : "3", gd->ram_size / SZ_1M);
308 void board_init_f(ulong dummy)
312 /* setup AIPS and disable watchdog */
315 /* iomux and setup of UART and SPI */
316 board_early_init_f();
321 /* UART clocks enabled and gd valid - init serial console */
322 preloader_console_init();
324 /* DDR initialization */
328 memset(__bss_start, 0, __bss_end - __bss_start);
330 /* Detect the board type */
333 /* load/boot image from boot device */
334 board_init_r(NULL, 0);
337 void board_boot_order(u32 *spl_boot_list)
339 u32 bootdev = spl_boot_device();
342 * The default boot fuse settings use the SD card (MMC1) as primary
343 * boot device, but allow SPI NOR as a fallback boot device. There
344 * is no proper way to detect if the fallback was used. Therefore
345 * we read the ECSPI2_CONREG register and see if it differs from the
346 * reset value 0x0. If that's the case we can assume that the BootROM
347 * has successfully probed the SPI NOR.
350 case BOOT_DEVICE_MMC1:
351 case BOOT_DEVICE_MMC2:
352 if (sl_mx6ul_is_spi_nor_boot()) {
353 spl_boot_list[0] = BOOT_DEVICE_SPI;
359 spl_boot_list[0] = bootdev;
362 int board_early_init_f(void)
365 if (sl_mx6ul_is_spi_nor_boot())
371 int board_fit_config_name_match(const char *name)
373 if (gd->board_type == BOARD_TYPE_KTN_SL_UL && is_mx6ul() &&
374 (!strcmp(name, "imx6ul-kontron-n631x-s") || !strcmp(name, "imx6ul-kontron-bl")))
377 if (gd->board_type == BOARD_TYPE_KTN_SL_ULL && is_mx6ull() &&
378 (!strcmp(name, "imx6ull-kontron-n641x-s") || !strcmp(name, "imx6ull-kontron-bl")))