board/kontron/sl-mx6ul/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Kontron Electronics GmbH
   4  */
   5
   6 #include <asm/arch/clock.h>
   7 #include <asm/arch/crm_regs.h>
   8 #include <asm/arch/mx6-pins.h>
   9 #include <asm/arch/sys_proto.h>
  10 #include <asm/global_data.h>
  11 #include <asm/gpio.h>
  12 #include <asm/io.h>
  13 #include <asm/mach-imx/iomux-v3.h>
  14 #include <fsl_esdhc_imx.h>
  15 #include <init.h>
  16 #include <linux/delay.h>
  17 #include <linux/sizes.h>
  18 #include <linux/errno.h>
  19 #include <mmc.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 enum {
  24         BOARD_TYPE_KTN_N631X = 1,
  25         BOARD_TYPE_KTN_N641X,
  26         BOARD_TYPE_MAX
  27 };
  28
  29 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  30         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  31         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  32
  33 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  34         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  35         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  36
  37 #define USDHC_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |  \
  38         PAD_CTL_PUS_100K_DOWN  | PAD_CTL_SPEED_LOW |            \
  39         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  42         PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  43
  44 #include <spl.h>
  45 #include <asm/arch/mx6-ddr.h>
  46
  47 static iomux_v3_cfg_t const usdhc1_pads[] = {
  48         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  49         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  50         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  51         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  52         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  53         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  54
  55         /* CD */
  56         MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
  57 };
  58
  59 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 19)
  60
  61 static iomux_v3_cfg_t const usdhc2_pads[] = {
  62         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  63         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  64         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68         /* RST */
  69         MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  70 };
  71
  72 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
  73
  74 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  75         {USDHC1_BASE_ADDR, 0, 4},
  76         {USDHC2_BASE_ADDR, 0, 4},
  77 };
  78
  79 int board_mmc_getcd(struct mmc *mmc)
  80 {
  81         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  82         int ret = 0;
  83
  84         switch (cfg->esdhc_base) {
  85         case USDHC1_BASE_ADDR:
  86                 ret = !gpio_get_value(USDHC1_CD_GPIO);
  87                 break;
  88         case USDHC2_BASE_ADDR:
  89                 // This SDHC interface does not use a CD pin
  90                 ret = 1;
  91                 break;
  92         }
  93
  94         return ret;
  95 }
  96
  97 int board_mmc_init(struct bd_info *bis)
  98 {
  99         int i, ret;
 100
 101         /*
 102          * According to the board_mmc_init() the following map is done:
 103          * (U-boot device node)    (Physical Port)
 104          * mmc0                    USDHC1
 105          * mmc1                    USDHC2
 106          */
 107         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 108                 switch (i) {
 109                 case 0:
 110                         imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 111                         gpio_direction_input(USDHC1_CD_GPIO);
 112                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 113                         break;
 114                 case 1:
 115                         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 116                         gpio_direction_output(USDHC2_PWR_GPIO, 0);
 117                         udelay(500);
 118                         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 119                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 120                         break;
 121                 default:
 122                         printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n",
 123                                i + 1);
 124                         return -EINVAL;
 125                         }
 126
 127                         ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 128                         if (ret) {
 129                                 printf("Warning: failed to initialize mmc dev %d\n", i);
 130                                 return ret;
 131                         }
 132         }
 133         return 0;
 134 }
 135
 136 iomux_v3_cfg_t const ecspi2_pads[] = {
 137         MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 138         MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 139         MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 140         MX6_PAD_CSI_DATA01__GPIO4_IO22  | MUX_PAD_CTRL(NO_PAD_CTRL),
 141 };
 142
 143 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
 144 {
 145         return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
 146                 ? (IMX_GPIO_NR(4, 22)) : -1;
 147 }
 148
 149 static void setup_spi(void)
 150 {
 151         gpio_request(IMX_GPIO_NR(4, 22), "spi2_cs0");
 152         gpio_direction_output(IMX_GPIO_NR(4, 22), 1);
 153         imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
 154
 155         enable_spi_clk(true, 1);
 156 }
 157
 158 static iomux_v3_cfg_t const uart4_pads[] = {
 159         MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 160         MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 161 };
 162
 163 static void setup_iomux_uart(void)
 164 {
 165         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 166 }
 167
 168 // DDR 256MB (Hynix H5TQ2G63DFR)
 169 static struct mx6_ddr3_cfg mem_256M_ddr = {
 170         .mem_speed = 800,
 171         .density = 2,
 172         .width = 16,
 173         .banks = 8,
 174         .rowaddr = 14,
 175         .coladdr = 10,
 176         .pagesz = 2,
 177         .trcd = 1350,
 178         .trcmin = 4950,
 179         .trasmin = 3600,
 180 };
 181
 182 static struct mx6_mmdc_calibration mx6_mmcd_256M_calib = {
 183         .p0_mpwldectrl0 = 0x00000000,
 184         .p0_mpdgctrl0 = 0x01340134,
 185         .p0_mprddlctl = 0x40405052,
 186         .p0_mpwrdlctl = 0x40404E48,
 187 };
 188
 189 // DDR 512MB (Hynix H5TQ4G63DFR)
 190 static struct mx6_ddr3_cfg mem_512M_ddr = {
 191         .mem_speed = 800,
 192         .density = 4,
 193         .width = 16,
 194         .banks = 8,
 195         .rowaddr = 15,
 196         .coladdr = 10,
 197         .pagesz = 2,
 198         .trcd = 1350,
 199         .trcmin = 4950,
 200         .trasmin = 3600,
 201 };
 202
 203 static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = {
 204         .p0_mpwldectrl0 = 0x00000000,
 205         .p0_mpdgctrl0 = 0X01440144,
 206         .p0_mprddlctl = 0x40405454,
 207         .p0_mpwrdlctl = 0x40404E4C,
 208 };
 209
 210 // Common DDR parameters (256MB and 512MB)
 211 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 212         .grp_addds = 0x00000028,
 213         .grp_ddrmode_ctl = 0x00020000,
 214         .grp_b0ds = 0x00000028,
 215         .grp_ctlds = 0x00000028,
 216         .grp_b1ds = 0x00000028,
 217         .grp_ddrpke = 0x00000000,
 218         .grp_ddrmode = 0x00020000,
 219         .grp_ddr_type = 0x000c0000,
 220 };
 221
 222 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 223         .dram_dqm0 = 0x00000028,
 224         .dram_dqm1 = 0x00000028,
 225         .dram_ras = 0x00000028,
 226         .dram_cas = 0x00000028,
 227         .dram_odt0 = 0x00000028,
 228         .dram_odt1 = 0x00000028,
 229         .dram_sdba2 = 0x00000000,
 230         .dram_sdclk_0 = 0x00000028,
 231         .dram_sdqs0 = 0x00000028,
 232         .dram_sdqs1 = 0x00000028,
 233         .dram_reset = 0x00000028,
 234 };
 235
 236 struct mx6_ddr_sysinfo ddr_sysinfo = {
 237         .dsize = 0,
 238         .cs_density = 20,
 239         .ncs = 1,
 240         .cs1_mirror = 0,
 241         .rtt_wr = 2,
 242         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 243         .walat = 1,             /* Write additional latency */
 244         .ralat = 5,             /* Read additional latency */
 245         .mif3_mode = 3,         /* Command prediction working mode */
 246         .bi_on = 1,             /* Bank interleaving enabled */
 247         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 248         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 249         .ddr_type = DDR_TYPE_DDR3,
 250         .refsel = 0,    /* Refresh cycles at 64KHz */
 251         .refr = 1,      /* 2 refresh commands per refresh cycle */
 252 };
 253
 254 static void ccgr_init(void)
 255 {
 256         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 257
 258         writel(0xFFFFFFFF, &ccm->CCGR0);
 259         writel(0xFFFFFFFF, &ccm->CCGR1);
 260         writel(0xFFFFFFFF, &ccm->CCGR2);
 261         writel(0xFFFFFFFF, &ccm->CCGR3);
 262         writel(0xFFFFFFFF, &ccm->CCGR4);
 263         writel(0xFFFFFFFF, &ccm->CCGR5);
 264         writel(0xFFFFFFFF, &ccm->CCGR6);
 265         writel(0xFFFFFFFF, &ccm->CCGR7);
 266 }
 267
 268 static void spl_dram_init(void)
 269 {
 270         unsigned int size;
 271
 272         // DDR RAM connection is always 16 bit wide. Init IOs.
 273         mx6ul_dram_iocfg(16, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 274
 275         // Try to detect the 512MB RAM chip first.
 276         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_512M_calib, &mem_512M_ddr);
 277
 278         // Get the available RAM size
 279         size = get_ram_size((void *)PHYS_SDRAM, SZ_512M);
 280
 281         gd->ram_size = size;
 282
 283         if (size == SZ_512M) {
 284                 // 512MB RAM was detected
 285                 return;
 286         } else if (size == SZ_256M) {
 287                 // 256MB RAM was detected, use correct config and calibration
 288                 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_256M_calib, &mem_256M_ddr);
 289         } else {
 290                 printf("Invalid DDR RAM size detected: %x\n", size);
 291         }
 292 }
 293
 294 static int do_board_detect(void)
 295 {
 296         if (is_mx6ul())
 297                 gd->board_type = BOARD_TYPE_KTN_N631X;
 298         else if (is_mx6ull())
 299                 gd->board_type = BOARD_TYPE_KTN_N641X;
 300
 301         printf("Kontron SL i.MX6UL%s (N6%s1x) module, %lu MB RAM detected\n",
 302                is_mx6ull() ? "L" : "", is_mx6ull() ? "4" : "3", gd->ram_size / SZ_1M);
 303
 304         return 0;
 305 }
 306
 307 void board_init_f(ulong dummy)
 308 {
 309         ccgr_init();
 310
 311         /* setup AIPS and disable watchdog */
 312         arch_cpu_init();
 313
 314         /* iomux and setup of UART and SPI */
 315         board_early_init_f();
 316
 317         /* setup GP timer */
 318         timer_init();
 319
 320         /* UART clocks enabled and gd valid - init serial console */
 321         preloader_console_init();
 322
 323         /* DDR initialization */
 324         spl_dram_init();
 325
 326         /* Clear the BSS. */
 327         memset(__bss_start, 0, __bss_end - __bss_start);
 328
 329         /* Detect the board type */
 330         do_board_detect();
 331
 332         /* load/boot image from boot device */
 333         board_init_r(NULL, 0);
 334 }
 335
 336 void board_boot_order(u32 *spl_boot_list)
 337 {
 338         u32 bootdev = spl_boot_device();
 339
 340         /*
 341          * The default boot fuse settings use the SD card (MMC1) as primary
 342          * boot device, but allow SPI NOR as a fallback boot device.
 343          * We can't detect the fallback case and spl_boot_device() will return
 344          * BOOT_DEVICE_MMC1 despite the actual boot device being SPI NOR.
 345          * Therefore we try to load U-Boot proper vom SPI NOR after loading
 346          * from MMC has failed.
 347          */
 348         spl_boot_list[0] = bootdev;
 349
 350         switch (bootdev) {
 351         case BOOT_DEVICE_MMC1:
 352         case BOOT_DEVICE_MMC2:
 353                 spl_boot_list[1] = BOOT_DEVICE_SPI;
 354                 break;
 355         }
 356 }
 357
 358 int board_early_init_f(void)
 359 {
 360         setup_iomux_uart();
 361         setup_spi();
 362
 363         return 0;
 364 }
 365
 366 int board_fit_config_name_match(const char *name)
 367 {
 368         if (gd->board_type == BOARD_TYPE_KTN_N631X && is_mx6ul() &&
 369             !strcmp(name, "imx6ul-kontron-n631x-s"))
 370                 return 0;
 371
 372         if (gd->board_type == BOARD_TYPE_KTN_N641X && is_mx6ull() &&
 373             !strcmp(name, "imx6ull-kontron-n641x-s"))
 374                 return 0;
 375
 376         return -1;
 377 }