1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Kontron Electronics GmbH
6 #include <asm/arch/clock.h>
7 #include <asm/arch/sys_proto.h>
8 #include <asm/global_data.h>
9 #include <fdt_support.h>
12 DECLARE_GLOBAL_DATA_PTR;
16 gd->ram_size = imx_ddr_size();
21 int ft_board_setup(void *blob, struct bd_info *bd)
24 * Overwrite the memory size in the devicetree that is
25 * passed to the kernel with the actual size detected.
27 return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size);
30 static int setup_fec(void)
32 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
36 * Use 50M anatop loopback REF_CLK1 for ENET1,
37 * clear gpr1[13], set gpr1[17].
39 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
40 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
43 * Use 50M anatop loopback REF_CLK2 for ENET2,
44 * clear gpr1[14], set gpr1[18].
46 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
47 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
49 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
53 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
60 int board_phy_config(struct phy_device *phydev)
62 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
64 if (phydev->drv->config)
65 phydev->drv->config(phydev);
70 int board_early_init_f(void)
79 /* Address of boot parameters */
80 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;