1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2020 Hitachi Power Grids. All rights reserved.
9 #include <asm/arch/immap_ls102xa.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/ls102xa_devdis.h>
13 #include <asm/arch/ls102xa_soc.h>
17 #include <fsl_esdhc.h>
19 #include <fsl_immap.h>
24 #include <fsl_devdis.h>
27 #include <fdt_support.h>
29 #include <fsl_validate.h>
31 #include "../common/common.h"
32 #include "../common/qrio.h"
34 DECLARE_GLOBAL_DATA_PTR;
36 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
47 return fsl_initdram();
50 int board_early_init_f(void)
52 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
53 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
54 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
56 /* Disable unused MCK1 */
57 setbits_be32(&gur->ddrclkdr, 2);
59 /* IFC Global Configuration */
60 setbits_be32(&ifc.gregs->ifc_gcr, 12 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
61 setbits_be32(&ifc.gregs->ifc_ccr, IFC_CCR_CLK_DIV(3) |
64 /* clear BD & FR bits for BE BD's and frame data */
65 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
66 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
68 init_early_memctl_regs();
70 /* QRIO Configuration */
71 qrio_uprstreq(UPREQ_CORE_RST);
73 #if CONFIG_IS_ENABLED(TARGET_PG_WCOM_SELI8)
74 qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
75 qrio_wdmask(KM_LIU_RST, true);
77 qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
78 qrio_wdmask(KM_PAXK_RST, true);
81 #if CONFIG_IS_ENABLED(TARGET_PG_WCOM_EXPU1)
82 qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST);
83 qrio_wdmask(WCOM_TMG_RST, true);
85 qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
86 qrio_prst(WCOM_PHY_RST, false, false);
88 qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST);
89 qrio_wdmask(WCOM_QSFP_RST, true);
91 qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST);
92 qrio_prst(WCOM_CLIPS_RST, false, false);
95 /* deasset debug phy reset only if piggy is present */
96 qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
97 qrio_prst(KM_DBG_ETH_RST, !qrio_get_pgy_pres_pin(), false);
99 i2c_deblock_gpio_cfg();
101 /* enable the Unit LED (red) & Boot LED (on) */
104 /* enable Application Buffer */
105 qrio_enable_app_buffer();
112 int misc_init_f(void)
114 if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED))
115 check_for_uboot_update();
121 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315))
126 ls102xa_smmu_stream_id_init();
133 int board_late_init(void)
138 int misc_init_r(void)
140 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
142 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
143 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
148 int ft_board_setup(void *blob, struct bd_info *bd)
150 ft_cpu_setup(blob, bd);
152 if (IS_ENABLED(CONFIG_PCI))
153 ft_pci_setup(blob, bd);
158 #if defined(CONFIG_POST)
159 int post_hotkeys_pressed(void)
161 /* DIC26_SELFTEST: QRIO, SLFTEST */
162 return qrio_get_selftest_pin();
165 /* POST word is located in the unused SCRATCHRW4 register */
166 #define CCSR_SCRATCHRW4_ADDR 0x1ee020c
168 ulong post_word_load(void)
170 void *addr = (void *)CCSR_SCRATCHRW4_ADDR;
171 return in_le32(addr);
174 void post_word_store(ulong value)
176 void *addr = (void *)CCSR_SCRATCHRW4_ADDR;
177 out_le32(addr, value);
180 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
182 /* Define only 1MiB range for mem_regions at the middle of the RAM */
183 /* For 1GiB range mem_regions takes approx. 4min */
184 *vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
190 u8 flash_read8(void *addr)
192 return __raw_readb(addr + 1);
195 void flash_write16(u16 val, void *addr)
197 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
199 __raw_writew(shftval, addr);
202 u16 flash_read16(void *addr)
204 u16 val = __raw_readw(addr);
206 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
209 int hush_init_var(void)
211 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
215 int last_stage_init(void)