1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2020 Hitachi Power Grids. All rights reserved.
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_devdis.h>
14 #include <asm/arch/ls102xa_soc.h>
18 #include <fsl_esdhc.h>
20 #include <fsl_immap.h>
25 #include <fsl_devdis.h>
28 #include <fdt_support.h>
30 #include <fsl_validate.h>
32 #include "../common/common.h"
33 #include "../common/qrio.h"
35 DECLARE_GLOBAL_DATA_PTR;
37 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
48 return fsl_initdram();
51 int board_early_init_f(void)
53 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
54 struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
55 struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
57 /* Disable unused MCK1 */
58 setbits_be32(&gur->ddrclkdr, 2);
60 /* IFC Global Configuration */
61 setbits_be32(&ifc.gregs->ifc_gcr, 12 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
62 setbits_be32(&ifc.gregs->ifc_ccr, IFC_CCR_CLK_DIV(3) |
65 /* clear BD & FR bits for BE BD's and frame data */
66 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
67 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
69 init_early_memctl_regs();
71 /* QRIO Configuration */
72 qrio_uprstreq(UPREQ_CORE_RST);
74 #if IS_ENABLED(CONFIG_TARGET_PG_WCOM_SELI8)
75 qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
76 qrio_wdmask(KM_LIU_RST, true);
78 qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
79 qrio_wdmask(KM_PAXK_RST, true);
82 #if IS_ENABLED(CONFIG_TARGET_PG_WCOM_EXPU1)
83 qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST);
84 qrio_wdmask(WCOM_TMG_RST, true);
86 qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
87 qrio_prst(WCOM_PHY_RST, false, false);
89 qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST);
90 qrio_wdmask(WCOM_QSFP_RST, true);
92 qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST);
93 qrio_prst(WCOM_CLIPS_RST, false, false);
96 /* deasset debug phy reset only if piggy is present */
97 qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
98 qrio_prst(KM_DBG_ETH_RST, !qrio_get_pgy_pres_pin(), false);
100 i2c_deblock_gpio_cfg();
102 /* enable the Unit LED (red) & Boot LED (on) */
105 /* enable Application Buffer */
106 qrio_enable_app_buffer();
113 static int pg_wcom_misc_init_f(void *ctx, struct event *event)
115 if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED))
116 check_for_uboot_update();
120 EVENT_SPY(EVT_MISC_INIT_F, pg_wcom_misc_init_f);
124 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315))
129 ls102xa_smmu_stream_id_init();
136 int board_late_init(void)
141 int misc_init_r(void)
143 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
145 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
146 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
151 int ft_board_setup(void *blob, struct bd_info *bd)
153 ft_cpu_setup(blob, bd);
155 if (IS_ENABLED(CONFIG_PCI))
156 ft_pci_setup(blob, bd);
161 #if defined(CONFIG_POST)
162 int post_hotkeys_pressed(void)
164 /* DIC26_SELFTEST: QRIO, SLFTEST */
165 return qrio_get_selftest_pin();
168 /* POST word is located in the unused SCRATCHRW4 register */
169 #define CCSR_SCRATCHRW4_ADDR 0x1ee020c
171 ulong post_word_load(void)
173 void *addr = (void *)CCSR_SCRATCHRW4_ADDR;
174 return in_le32(addr);
177 void post_word_store(ulong value)
179 void *addr = (void *)CCSR_SCRATCHRW4_ADDR;
180 out_le32(addr, value);
183 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
185 /* Define only 1MiB range for mem_regions at the middle of the RAM */
186 /* For 1GiB range mem_regions takes approx. 4min */
187 *vstart = CFG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
193 u8 flash_read8(void *addr)
195 return __raw_readb(addr + 1);
198 void flash_write16(u16 val, void *addr)
200 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
202 __raw_writew(shftval, addr);
205 u16 flash_read16(void *addr)
207 u16 val = __raw_readw(addr);
209 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
212 int hush_init_var(void)
214 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
218 int last_stage_init(void)