3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
31 extern int ivm_read_eeprom (void);
33 DECLARE_GLOBAL_DATA_PTR;
35 const uint sdram_table[] =
37 0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00,
38 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
40 0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
41 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
42 /* 0x10 Load mode register */
43 0x0ffffc34, 0x0ff57c04, 0x0ffffc04, 0x1ffffc05,
44 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
45 /* 0x18 Single Write */
46 0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04,
47 0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04,
48 /* 0x20 Burst Write */
49 0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
50 0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04,
51 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
52 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
53 /* 0x30 Precharge all and Refresh */
54 0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04,
55 0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04,
56 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
58 0x7ffffc04, 0xfffffc07, 0xfffffc04, 0xfffffc04,
63 puts ("Board: Keymile mgsuvd\n");
67 phys_size_t initdram (int board_type)
69 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
70 volatile memctl8xx_t *memctl = &immap->im_memctl;
73 upmconfig (UPMB, (uint *) sdram_table,
74 sizeof (sdram_table) / sizeof (uint));
77 * Preliminary prescaler for refresh (depends on number of
78 * banks): This value is selected for four cycles every 62.4 us
79 * with two SDRAM banks or four cycles every 31.2 us with one
80 * bank. It will be adjusted after memory sizing.
82 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
85 * The following value is used as an address (i.e. opcode) for
86 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
87 * the port size is 32bit the SDRAM does NOT "see" the lower two
88 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
91 * | | | | +- Burst Length = 4
92 * | | | +----- Burst Type = Sequential
93 * | | +------- CAS Latency = 2
94 * | +----------- Operating Mode = Standard
95 * +-------------- Write Burst Mode = Programmed Burst Length
97 memctl->memc_mar = CONFIG_SYS_MAR;
100 * Map controller banks 1 to the SDRAM banks 1 at
101 * preliminary addresses - these have to be modified after the
102 * SDRAM size has been determined.
104 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
105 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
107 memctl->memc_mbmr = CONFIG_SYS_MBMR & (~(MBMR_PTBE)); /* no refresh yet */
111 /* perform SDRAM initializsation sequence */
113 memctl->memc_mcr = 0x80802830; /* SDRAM bank 0 */
115 memctl->memc_mcr = 0x80802110; /* SDRAM bank 0 - execute twice */
118 memctl->memc_mbmr |= MBMR_PTBE; /* enable refresh */
123 * Check Bank 0 Memory Size for re-configuration
126 size = get_ram_size(SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
130 debug ("SDRAM Bank 0: %ld MB\n", size >> 20);
136 * Early board initalization.
138 int board_early_init_r(void)
140 /* setup the UPIOx */
141 out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc0);
142 out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x35);
146 int hush_init_var (void)
152 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
153 extern int fdt_set_node_and_value (void *blob,
160 * update "memory" property in the blob
162 void ft_blob_update (void *blob, bd_t *bd)
164 ulong brg_data[1] = {0};
165 ulong memory_data[2] = {0};
166 ulong flash_data[4] = {0};
168 memory_data[0] = cpu_to_be32 (bd->bi_memstart);
169 memory_data[1] = cpu_to_be32 (bd->bi_memsize);
170 fdt_set_node_and_value (blob, "/memory", "reg", memory_data,
171 sizeof (memory_data));
173 flash_data[2] = cpu_to_be32 (bd->bi_flashstart);
174 flash_data[3] = cpu_to_be32 (bd->bi_flashsize);
175 fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data,
176 sizeof (flash_data));
179 brg_data[0] = cpu_to_be32 (bd->bi_busfreq);
180 fdt_set_node_and_value (blob, "/soc/cpm", "brg-frequency", brg_data,
184 fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address",
185 bd->bi_enetaddr, sizeof (u8) * 6);
188 void ft_board_setup(void *blob, bd_t *bd)
190 ft_cpu_setup (blob, bd);
191 ft_blob_update (blob, bd);
193 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
195 int i2c_soft_read_pin (void)
199 *(unsigned short *)(I2C_BASE_DIR) &= ~SDA_CONF;
201 val = *(unsigned char *)(I2C_BASE_PORT);
203 return ((val & SDA_BIT) == SDA_BIT);