1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 Keymile AG
4 * Valentin Longchamp <valentin.longchamp@keymile.com>
9 #include "../common/common.h"
12 /* QRIO GPIO register offsets */
13 #define DIRECT_OFF 0x18
16 int qrio_get_gpio(u8 port_off, u8 gpio_nr)
20 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
22 gprt = in_be32(qrio_base + port_off + GPRT_OFF);
24 return (gprt >> gpio_nr) & 1U;
27 void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value)
31 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
35 gprt = in_be32(qrio_base + port_off + GPRT_OFF);
41 out_be32(qrio_base + port_off + GPRT_OFF, gprt);
44 void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value)
48 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
52 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
54 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
56 qrio_set_gpio(port_off, gpio_nr, value);
59 void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr)
63 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
67 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
69 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
72 void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
76 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
80 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
82 /* set to output -> GPIO drives low */
85 /* set to input -> GPIO floating */
88 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
91 #define WDMASK_OFF 0x16
93 void qrio_wdmask(u8 bit, bool wden)
96 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
98 wdmask = in_be16(qrio_base + WDMASK_OFF);
101 wdmask |= (1 << bit);
103 wdmask &= ~(1 << bit);
105 out_be16(qrio_base + WDMASK_OFF, wdmask);
108 #define PRST_OFF 0x1a
110 void qrio_prst(u8 bit, bool en, bool wden)
113 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
115 qrio_wdmask(bit, wden);
117 prst = in_be16(qrio_base + PRST_OFF);
124 out_be16(qrio_base + PRST_OFF, prst);
127 #define PRSTCFG_OFF 0x1c
129 void qrio_prstcfg(u8 bit, u8 mode)
133 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
135 prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
137 for (i = 0; i < 2; i++) {
139 set_bit(2*bit+i, &prstcfg);
141 clear_bit(2*bit+i, &prstcfg);
144 out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
147 #define CTRLH_OFF 0x02
148 #define CTRLH_WRL_BOOT 0x01
149 #define CTRLH_WRL_UNITRUN 0x02
151 void qrio_set_leds(void)
154 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
156 /* set UNIT LED to RED and BOOT LED to ON */
157 ctrlh = in_8(qrio_base + CTRLH_OFF);
158 ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN);
159 out_8(qrio_base + CTRLH_OFF, ctrlh);
162 #define CTRLL_OFF 0x03
163 #define CTRLL_WRB_BUFENA 0x20
165 void qrio_enable_app_buffer(void)
168 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
170 /* enable application buffer */
171 ctrll = in_8(qrio_base + CTRLL_OFF);
172 ctrll |= (CTRLL_WRB_BUFENA);
173 out_8(qrio_base + CTRLL_OFF, ctrll);
176 #define REASON1_OFF 0x12
177 #define REASON1_CPUWD 0x01
179 void qrio_cpuwd_flag(bool flag)
182 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
183 reason1 = in_8(qrio_base + REASON1_OFF);
185 reason1 |= REASON1_CPUWD;
187 reason1 &= ~REASON1_CPUWD;
188 out_8(qrio_base + REASON1_OFF, reason1);
191 #define RSTCFG_OFF 0x11
193 void qrio_uprstreq(u8 mode)
196 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
198 rstcfg = in_8(qrio_base + RSTCFG_OFF);
200 if (mode & UPREQ_CORE_RST)
201 rstcfg |= UPREQ_CORE_RST;
203 rstcfg &= ~UPREQ_CORE_RST;
205 out_8(qrio_base + RSTCFG_OFF, rstcfg);