2 * (C) Copyright 2013 Keymile AG
3 * Valentin Longchamp <valentin.longchamp@keymile.com>
5 * Copyright 2011,2012 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/compiler.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
17 #include <asm/immap_85xx.h>
18 #include <asm/fsl_law.h>
19 #include <asm/fsl_serdes.h>
20 #include <asm/fsl_portals.h>
21 #include <asm/fsl_liodn.h>
24 #include "../common/common.h"
27 DECLARE_GLOBAL_DATA_PTR;
31 printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
36 /* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
37 * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
38 * For I2C only the low state is activly driven and high state is pulled-up
39 * by a resistor. Therefore the deblock GPIOs are used
40 * -> as an active output to drive a low state
41 * -> as an open-drain input to have a pulled-up high state
44 /* QRIO GPIOs used for deblocking */
45 #define DEBLOCK_PORT1 GPIO_A
46 #define DEBLOCK_SCL1 20
47 #define DEBLOCK_SDA1 21
49 /* By default deblock GPIOs are floating */
50 static void i2c_deblock_gpio_cfg(void)
52 /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
53 qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
54 qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
56 qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
57 qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
60 void set_sda(int state)
62 qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
65 void set_scl(int state)
67 qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
72 return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
77 return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
83 #define RSTRQSR1_WDT_RR 0x00200000
84 #define RSTRQSR1_SW_RR 0x00100000
86 int board_early_init_f(void)
88 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
89 bool cpuwd_flag = false;
91 /* configure mode for uP reset request */
92 qrio_uprstreq(UPREQ_CORE_RST);
94 /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
95 setbits_be32(&gur->ddrclkdr, 0x001f000f);
97 /* set reset reason according CPU register */
98 if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
102 qrio_cpuwd_flag(cpuwd_flag);
103 /* clear CPU bits by writing 1 */
104 setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
106 /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
107 qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
108 /* and enable WD on it */
109 qrio_wdmask(BFTIC4_RST, true);
111 /* set the ZL30138's prstcfg to reset at power-up and unit reset only */
112 qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_UNIT_RST);
113 /* and take it out of reset as soon as possible (needed for Hooper) */
114 qrio_prst(ZL30158_RST, false, false);
119 int board_early_init_r(void)
122 /* Flush d-cache and invalidate i-cache of any FLASH data */
129 ret = trigger_fpga_config();
131 printf("error triggering PCIe FPGA config\n");
133 /* enable the Unit LED (red) & Boot LED (on) */
136 /* enable Application Buffer */
137 qrio_enable_app_buffer();
142 unsigned long get_board_sys_clk(unsigned long dummy)
147 #define ETH_FRONT_PHY_RST 15
150 #define ZL30343_RST 9
152 int misc_init_f(void)
154 /* configure QRIO pis for i2c deblocking */
155 i2c_deblock_gpio_cfg();
157 /* configure the front phy's prstcfg and take it out of reset */
158 qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
159 qrio_prst(ETH_FRONT_PHY_RST, false, false);
161 /* set the ZL30343 prstcfg to reset at power-up and unit reset only */
162 qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_UNIT_RST);
163 /* and enable the WD on it */
164 qrio_wdmask(ZL30343_RST, true);
166 /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
167 qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
168 qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
170 /* and enable the WD on them */
171 qrio_wdmask(QSFP1_RST, true);
172 qrio_wdmask(QSFP2_RST, true);
177 #define NUM_SRDS_BANKS 2
179 int misc_init_r(void)
181 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
182 u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
183 SRDS_PLLCR0_RFCK_SEL_125};
186 /* check SERDES reference clocks */
187 for (i = 0; i < NUM_SRDS_BANKS; i++) {
188 u32 actual = in_be32(®s->bank[i].pllcr0);
189 actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
190 if (actual != expected[i]) {
191 printf("Warning: SERDES bank %u expects reference \
192 clock %sMHz, but actual is %sMHz\n", i + 1,
193 serdes_clock_to_string(expected[i]),
194 serdes_clock_to_string(actual));
201 #if defined(CONFIG_HUSH_INIT_VAR)
202 int hush_init_var(void)
209 #if defined(CONFIG_LAST_STAGE_INIT)
211 int last_stage_init(void)
213 #if defined(CONFIG_KMCOGE4)
214 /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
215 struct bfticu_iomap *bftic4 =
216 (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
217 u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
219 if (dip_switch != 0) {
220 /* start bootloader */
221 puts("DIP: Enabled\n");
222 setenv("actual_bank", "0");
231 #ifdef CONFIG_SYS_DPAA_FMAN
232 void fdt_fixup_fman_mac_addresses(void *blob)
236 unsigned char mac_addr[6];
238 /* get the mac addr from env */
239 tmp = getenv("ethaddr");
241 printf("ethaddr env variable not defined\n");
244 for (i = 0; i < 6; i++) {
245 mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
247 tmp = (*end) ? end+1 : end;
250 /* find the correct fdt ethernet path and correct it */
251 node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
253 printf("no /soc/fman/ethernet path offset\n");
256 ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
258 printf("error setting local-mac-address property\n");
264 void ft_board_setup(void *blob, bd_t *bd)
269 ft_cpu_setup(blob, bd);
271 base = getenv_bootm_low();
272 size = getenv_bootm_size();
274 fdt_fixup_memory(blob, (u64)base, (u64)size);
276 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
277 fdt_fixup_dr_usb(blob, bd);
281 pci_of_setup(blob, bd);
284 fdt_fixup_liodn(blob);
285 #ifdef CONFIG_SYS_DPAA_FMAN
286 fdt_fixup_fman_ethernet(blob);
287 fdt_fixup_fman_mac_addresses(blob);
291 #if defined(CONFIG_POST)
293 /* DIC26_SELFTEST GPIO used to start factory test sw */
294 #define SELFTEST_PORT GPIO_A
295 #define SELFTEST_PIN 31
297 int post_hotkeys_pressed(void)
299 qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
300 return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);