1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 Keymile AG
4 * Valentin Longchamp <valentin.longchamp@keymile.com>
6 * Copyright 2011,2012 Freescale Semiconductor, Inc.
12 #include <fdt_support.h>
15 #include <linux/compiler.h>
17 #include <asm/processor.h>
18 #include <asm/cache.h>
19 #include <asm/immap_85xx.h>
20 #include <asm/fsl_law.h>
21 #include <asm/fsl_serdes.h>
22 #include <asm/fsl_portals.h>
23 #include <asm/fsl_liodn.h>
26 #include "../common/common.h"
27 #include "../common/qrio.h"
30 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
34 printf("Board: Keymile %s\n", CONFIG_SYS_CONFIG_NAME);
41 #define RSTRQSR1_WDT_RR 0x00200000
42 #define RSTRQSR1_SW_RR 0x00100000
44 int board_early_init_f(void)
46 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
47 bool cpuwd_flag = false;
49 /* configure mode for uP reset request */
50 qrio_uprstreq(UPREQ_CORE_RST);
52 /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
53 setbits_be32(&gur->ddrclkdr, 0x001f000f);
55 /* set reset reason according CPU register */
56 if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
60 qrio_cpuwd_flag(cpuwd_flag);
61 /* clear CPU bits by writing 1 */
62 setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
64 /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
65 qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
66 /* and enable WD on it */
67 qrio_wdmask(BFTIC4_RST, true);
69 /* set the ZL30138's prstcfg to reset at power-up only */
70 qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
71 /* and take it out of reset as soon as possible (needed for Hooper) */
72 qrio_prst(ZL30158_RST, false, false);
77 int board_early_init_r(void)
80 /* Flush d-cache and invalidate i-cache of any FLASH data */
85 setup_qbman_portals();
87 ret = trigger_fpga_config();
89 printf("error triggering PCIe FPGA config\n");
91 /* enable the Unit LED (red) & Boot LED (on) */
94 /* enable Application Buffer */
95 qrio_enable_app_buffer();
100 unsigned long get_board_sys_clk(unsigned long dummy)
105 #define ETH_FRONT_PHY_RST 15
108 #define ZL30343_RST 9
110 int misc_init_f(void)
112 /* configure QRIO pis for i2c deblocking */
113 i2c_deblock_gpio_cfg();
115 /* configure the front phy's prstcfg and take it out of reset */
116 qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
117 qrio_prst(ETH_FRONT_PHY_RST, false, false);
119 /* set the ZL30343 prstcfg to reset at power-up only */
120 qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
121 /* and enable the WD on it */
122 qrio_wdmask(ZL30343_RST, true);
124 /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
125 qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
126 qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
128 /* and enable the WD on them */
129 qrio_wdmask(QSFP1_RST, true);
130 qrio_wdmask(QSFP2_RST, true);
135 #define NUM_SRDS_BANKS 2
137 int misc_init_r(void)
139 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
140 u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
141 SRDS_PLLCR0_RFCK_SEL_125};
144 /* check SERDES reference clocks */
145 for (i = 0; i < NUM_SRDS_BANKS; i++) {
146 u32 actual = in_be32(®s->bank[i].pllcr0);
147 actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
148 if (actual != expected[i]) {
149 printf("Warning: SERDES bank %u expects reference \
150 clock %sMHz, but actual is %sMHz\n", i + 1,
151 serdes_clock_to_string(expected[i]),
152 serdes_clock_to_string(actual));
156 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
157 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
161 #if defined(CONFIG_HUSH_INIT_VAR)
162 int hush_init_var(void)
164 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
169 #if defined(CONFIG_LAST_STAGE_INIT)
171 int last_stage_init(void)
173 #if defined(CONFIG_KMCOGE4)
174 /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
175 struct bfticu_iomap *bftic4 =
176 (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
177 u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
179 if (dip_switch != 0) {
180 /* start bootloader */
181 puts("DIP: Enabled\n");
182 env_set("actual_bank", "0");
191 #ifdef CONFIG_SYS_DPAA_FMAN
192 void fdt_fixup_fman_mac_addresses(void *blob)
196 unsigned char mac_addr[6];
198 /* get the mac addr from env */
199 tmp = env_get("ethaddr");
201 printf("ethaddr env variable not defined\n");
204 for (i = 0; i < 6; i++) {
205 mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
207 tmp = (*end) ? end+1 : end;
210 /* find the correct fdt ethernet path and correct it */
211 node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
213 printf("no /soc/fman/ethernet path offset\n");
216 ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
218 printf("error setting local-mac-address property\n");
224 int ft_board_setup(void *blob, bd_t *bd)
229 ft_cpu_setup(blob, bd);
231 base = env_get_bootm_low();
232 size = env_get_bootm_size();
234 fdt_fixup_memory(blob, (u64)base, (u64)size);
236 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
237 fsl_fdt_fixup_dr_usb(blob, bd);
241 pci_of_setup(blob, bd);
244 fdt_fixup_liodn(blob);
245 #ifdef CONFIG_SYS_DPAA_FMAN
246 fdt_fixup_fman_ethernet(blob);
247 fdt_fixup_fman_mac_addresses(blob);
253 #if defined(CONFIG_POST)
255 /* DIC26_SELFTEST GPIO used to start factory test sw */
256 #define SELFTEST_PORT QRIO_GPIO_A
257 #define SELFTEST_PIN 31
259 int post_hotkeys_pressed(void)
261 qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
262 return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);