board/keymile/kmcent2/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Keymile AG
   4  * Rainer Boschung <rainer.boschung@keymile.com>
   5  *
   6  * Copyright 2013 Freescale Semiconductor, Inc.
   7  */
   8
   9 #include <asm/fsl_law.h>
  10 #include <asm/mmu.h>
  11 #include <asm/mpc85xx_gpio.h>
  12 #include <fsl_ddr_sdram.h>
  13 #include <fsl_ddr_dimm_params.h>
  14 #include <hwconfig.h>
  15 #include <i2c.h>
  16 #include <init.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 #define DQSn_POS(n)             (3 - (((n) - 1) % 4)) * 8
  21 #define DQSn_START(n, start)    ((start) << DQSn_POS(n))
  22
  23 void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
  24                            unsigned int ctrl_num)
  25 {
  26         if (ctrl_num > 1) {
  27                 printf("Not supported controller number %d\n", ctrl_num);
  28                 return;
  29         }
  30
  31         /* 1/2 clk delay between wr command and data strobe */
  32         popts->write_data_delay = 4;
  33         /* clk lauched 1/2 applied cylcle after address command */
  34         popts->clk_adjust = 4;
  35         /* 1T timing: command/address held for only 1 cycle */
  36         popts->twot_en = 0;
  37         popts->threet_en = 0;
  38
  39         /* optimize cpo for erratum A-009942 */
  40         popts->cpo_sample = 0x3b;
  41
  42         /* we have only one module, half str should be OK */
  43         popts->half_strength_driver_enable = 1;
  44         /*
  45          * Write leveling override
  46          */
  47         /* set for DDR3-1600 */
  48         popts->wrlvl_override = 1;
  49         popts->wrlvl_sample = 0xf;
  50         popts->wrlvl_start = 0x7;
  51         /* DQS write leveling start time according layout */
  52         popts->wrlvl_ctl_2 = (DQSn_START(1, 0x06) |
  53                               DQSn_START(2, 0x06) |
  54                               DQSn_START(3, 0x07) |
  55                               DQSn_START(4, 0x07));
  56         popts->wrlvl_ctl_3 = (DQSn_START(5, 0x07) |
  57                               DQSn_START(6, 0x08) |
  58                               DQSn_START(7, 0x08) |
  59                               DQSn_START(8, 0x08));
  60
  61         /*
  62          * rtt and wtt_wr override
  63          */
  64         popts->rtt_override = 0;
  65
  66         /* Enable ZQ calibration */
  67         popts->zq_en = 1;
  68
  69         /* DHC_EN =1, ODT = 75 Ohm */
  70         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  71         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  72 }
  73
  74 int dram_init(void)
  75 {
  76         phys_size_t dram_size;
  77
  78         puts("Initializing....using SPD\n");
  79
  80         dram_size = fsl_ddr_sdram();
  81
  82         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  83         dram_size *= 0x100000;
  84
  85         gd->ram_size = dram_size;
  86
  87         return 0;
  88 }