3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
37 #include <asm/arch/kirkwood.h>
38 #include <asm/arch/mpp.h>
40 #include "../common/common.h"
42 DECLARE_GLOBAL_DATA_PTR;
45 * BOCO FPGA definitions
48 #define REG_CTRL_H 0x02
49 #define MASK_WRL_UNITRUN 0x01
50 #define MASK_RBX_PGY_PRESENT 0x40
51 #define REG_IRQ_CIRQ2 0x2d
52 #define MASK_RBI_DEFECT_16 0x01
54 /* Multi-Purpose Pins Functionality configuration */
55 u32 kwmpp_config[] = {
64 #if defined(CONFIG_SOFT_I2C)
68 #if defined(CONFIG_HARD_I2C)
74 MPP12_GPO, /* Reserved */
77 MPP15_GPIO, /* Not used */
78 MPP16_GPIO, /* Not used */
79 MPP17_GPIO, /* Reserved */
96 MPP34_GPIO, /* CDL1 (input) */
97 MPP35_GPIO, /* CDL2 (input) */
98 MPP36_GPIO, /* MAIN_IRQ (input) */
99 MPP37_GPIO, /* BOARD_LED */
100 MPP38_GPIO, /* Piggy3 LED[1] */
101 MPP39_GPIO, /* Piggy3 LED[2] */
102 MPP40_GPIO, /* Piggy3 LED[3] */
103 MPP41_GPIO, /* Piggy3 LED[4] */
104 MPP42_GPIO, /* Piggy3 LED[5] */
105 MPP43_GPIO, /* Piggy3 LED[6] */
106 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
107 MPP45_GPIO, /* Piggy3 LED[8] */
108 MPP46_GPIO, /* Reserved */
109 MPP47_GPIO, /* Reserved */
110 MPP48_GPIO, /* Reserved */
111 MPP49_GPIO, /* SW_INTOUTn */
115 #if defined(CONFIG_MGCOGE3UN)
117 * Wait for startup OK from mgcoge3ne
119 int startup_allowed(void)
124 * Read CIRQ16 bit (bit 0)
126 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
127 printf("%s: Error reading Boco\n", __func__);
129 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
135 * mgcoge3un has always ethernet present. Its connected to the 6061 switch
136 * and provides ICNev and piggy4 connections.
138 int ethernet_present(void)
143 int ethernet_present(void)
148 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
149 printf("%s: Error reading Boco\n", __func__);
152 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
159 int initialize_unit_leds(void)
162 * Init the unit LEDs per default they all are
163 * ok apart from bootstat
167 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
168 printf("%s: Error reading Boco\n", __func__);
171 buf |= MASK_WRL_UNITRUN;
172 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
173 printf("%s: Error writing Boco\n", __func__);
179 #if defined(CONFIG_BOOTCOUNT_LIMIT)
180 void set_bootcount_addr(void)
183 unsigned int bootcountaddr;
184 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
185 sprintf((char *)buf, "0x%x", bootcountaddr);
186 setenv("bootcountaddr", (char *)buf);
190 int misc_init_r(void)
195 str = getenv("mach_type");
197 mach_type = simple_strtoul(str, NULL, 10);
198 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
199 gd->bd->bi_arch_number = mach_type;
201 #if defined(CONFIG_MGCOGE3UN)
203 wait_for_ne = getenv("waitforne");
204 if (wait_for_ne != NULL) {
205 if (strcmp(wait_for_ne, "true") == 0) {
208 while (startup_allowed() == 0) {
212 puts("wait\b\b\b\b");
223 initialize_unit_leds();
225 #if defined(CONFIG_BOOTCOUNT_LIMIT)
226 set_bootcount_addr();
231 int board_early_init_f(void)
235 kirkwood_mpp_conf(kwmpp_config);
238 * The FLASH_GPIO_PIN switches between using a
239 * NAND or a SPI FLASH. Set this pin on start
242 tmp = readl(KW_GPIO0_BASE);
243 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
244 tmp = readl(KW_GPIO0_BASE + 4);
245 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
247 #if defined(CONFIG_SOFT_I2C)
248 /* init the GPIO for I2C Bitbang driver */
249 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
250 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
251 kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
252 kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
254 #if defined(CONFIG_SYS_EEPROM_WREN)
255 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
256 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
265 * arch number of board
267 gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
269 /* address of boot parameters */
270 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
275 #if defined(CONFIG_CMD_SF)
276 int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
280 return cmd_usage(cmdtp);
282 if ((strcmp(argv[1], "off") == 0)) {
283 printf("SPI FLASH disabled, NAND enabled\n");
284 /* Multi-Purpose Pins Functionality configuration */
285 kwmpp_config[0] = MPP0_NF_IO2;
286 kwmpp_config[1] = MPP1_NF_IO3;
287 kwmpp_config[2] = MPP2_NF_IO4;
288 kwmpp_config[3] = MPP3_NF_IO5;
290 kirkwood_mpp_conf(kwmpp_config);
291 tmp = readl(KW_GPIO0_BASE);
292 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
293 } else if ((strcmp(argv[1], "on") == 0)) {
294 printf("SPI FLASH enabled, NAND disabled\n");
295 /* Multi-Purpose Pins Functionality configuration */
296 kwmpp_config[0] = MPP0_SPI_SCn;
297 kwmpp_config[1] = MPP1_SPI_MOSI;
298 kwmpp_config[2] = MPP2_SPI_SCK;
299 kwmpp_config[3] = MPP3_SPI_MISO;
301 kirkwood_mpp_conf(kwmpp_config);
302 tmp = readl(KW_GPIO0_BASE);
303 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
305 return cmd_usage(cmdtp);
312 spitoggle, 2, 0, do_spi_toggle,
313 "En-/disable SPI FLASH access",
314 "<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
320 /* dram_init must store complete ramsize in gd->ram_size */
322 gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0),
327 void dram_init_banksize(void)
331 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
332 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
333 gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
338 #if defined(CONFIG_MGCOGE3UN)
340 #define PHY_LED_SEL 0x18
341 #define PHY_LED0_LINK (0x5)
342 #define PHY_LED1_ACT (0x8<<4)
343 #define PHY_LED2_INT (0xe<<8)
344 #define PHY_SPEC_CTRL 0x1c
345 #define PHY_RGMII_CLK_STABLE (0x1<<10)
346 #define PHY_CLSA (0x1<<1)
348 /* Configure and enable MV88E3018 PHY */
351 char *name = "egiga0";
354 if (miiphy_set_current_dev(name))
357 /* RGMII clk transition on data stable */
358 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0)
359 printf("Error reading PHY spec ctrl reg\n");
360 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL,
361 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0)
362 printf("Error writing PHY spec ctrl reg\n");
365 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL,
366 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0)
367 printf("Error writing PHY LED reg\n");
370 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
373 /* Configure and enable MV88E1118 PHY on the piggy*/
376 char *name = "egiga0";
378 if (miiphy_set_current_dev(name))
382 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
387 #if defined(CONFIG_HUSH_INIT_VAR)
388 int hush_init_var(void)
395 #if defined(CONFIG_BOOTCOUNT_LIMIT)
396 void bootcount_store(ulong a)
398 volatile ulong *save_addr;
399 volatile ulong size = 0;
401 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
402 size += gd->bd->bi_dram[i].size;
404 save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
405 writel(a, save_addr);
406 writel(BOOTCOUNT_MAGIC, &save_addr[1]);
409 ulong bootcount_load(void)
411 volatile ulong *save_addr;
412 volatile ulong size = 0;
414 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
415 size += gd->bd->bi_dram[i].size;
417 save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
418 if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
421 return readl(save_addr);
425 #if defined(CONFIG_SOFT_I2C)
426 void set_sda(int state)
432 void set_scl(int state)
445 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
449 #if defined(CONFIG_SYS_EEPROM_WREN)
450 int eeprom_write_enable(unsigned dev_addr, int state)
452 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
454 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);