1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Prafulla Wadaskar <prafulla@marvell.com>
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
11 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
24 #include <asm/arch/cpu.h>
25 #include <asm/arch/soc.h>
26 #include <asm/arch/mpp.h>
28 #include "../common/common.h"
30 DECLARE_GLOBAL_DATA_PTR;
33 * BOCO FPGA definitions
36 #define REG_CTRL_H 0x02
37 #define MASK_WRL_UNITRUN 0x01
38 #define MASK_RBX_PGY_PRESENT 0x40
39 #define REG_IRQ_CIRQ2 0x2d
40 #define MASK_RBI_DEFECT_16 0x01
43 * PHY registers definitions
45 #define PHY_MARVELL_OUI 0x5043
46 #define PHY_MARVELL_88E1118_MODEL 0x0022
47 #define PHY_MARVELL_88E1118R_MODEL 0x0024
49 #define PHY_MARVELL_PAGE_REG 0x0016
50 #define PHY_MARVELL_DEFAULT_PAGE 0x0000
52 #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003
53 #define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010
55 #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000
56 #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0)
57 #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4)
58 #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8)
60 /* I/O pin to erase flash RGPP09 = MPP43 */
61 #define KM_FLASH_ERASE_ENABLE 43
63 /* Multi-Purpose Pins Functionality configuration */
64 static const u32 kwmpp_config[] = {
72 #if defined(KM_PCIE_RESET_MPP7)
77 #if defined(CONFIG_SYS_I2C_SOFT)
83 MPP12_GPO, /* Reserved */
86 MPP15_GPIO, /* Not used */
87 MPP16_GPIO, /* Not used */
88 MPP17_GPIO, /* Reserved */
105 MPP34_GPIO, /* CDL1 (input) */
106 MPP35_GPIO, /* CDL2 (input) */
107 MPP36_GPIO, /* MAIN_IRQ (input) */
108 MPP37_GPIO, /* BOARD_LED */
109 MPP38_GPIO, /* Piggy3 LED[1] */
110 MPP39_GPIO, /* Piggy3 LED[2] */
111 MPP40_GPIO, /* Piggy3 LED[3] */
112 MPP41_GPIO, /* Piggy3 LED[4] */
113 MPP42_GPIO, /* Piggy3 LED[5] */
114 MPP43_GPIO, /* Piggy3 LED[6] */
115 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
116 MPP45_GPIO, /* Piggy3 LED[8] */
117 MPP46_GPIO, /* Reserved */
118 MPP47_GPIO, /* Reserved */
119 MPP48_GPIO, /* Reserved */
120 MPP49_GPIO, /* SW_INTOUTn */
124 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
126 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
128 * All boards with PIGGY4 connected via a simple switch have ethernet always
131 int ethernet_present(void)
136 int ethernet_present(void)
141 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
142 printf("%s: Error reading Boco\n", __func__);
145 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
152 static int initialize_unit_leds(void)
155 * Init the unit LEDs per default they all are
156 * ok apart from bootstat
160 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
161 printf("%s: Error reading Boco\n", __func__);
164 buf |= MASK_WRL_UNITRUN;
165 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
166 printf("%s: Error writing Boco\n", __func__);
172 static void set_bootcount_addr(void)
175 unsigned int bootcountaddr;
176 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
177 sprintf((char *)buf, "0x%x", bootcountaddr);
178 env_set("bootcountaddr", (char *)buf);
181 int misc_init_r(void)
183 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
184 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
186 initialize_unit_leds();
188 set_bootcount_addr();
192 int board_early_init_f(void)
194 #if defined(CONFIG_SYS_I2C_SOFT)
197 /* set the 2 bitbang i2c pins as output gpios */
198 tmp = readl(MVEBU_GPIO0_BASE + 4);
199 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
201 /* adjust SDRAM size for bank 0 */
202 mvebu_sdram_size_adjust(0);
203 kirkwood_mpp_conf(kwmpp_config, NULL);
209 /* address of boot parameters */
210 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
213 * The KM_FLASH_GPIO_PIN switches between using a
214 * NAND or a SPI FLASH. Set this pin on start
217 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
218 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
220 #if defined(CONFIG_SYS_I2C_SOFT)
222 * Reinit the GPIO for I2C Bitbang driver so that the now
223 * available gpio framework is consistent. The calls to
224 * direction output in are not necessary, they are already done in
227 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
228 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
231 #if defined(CONFIG_SYS_EEPROM_WREN)
232 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
233 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
236 #if defined(CONFIG_KM_FPGA_CONFIG)
237 trigger_fpga_config();
243 int board_late_init(void)
245 #if defined(CONFIG_KM_COGE5UN)
246 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
248 /* if pin 1 do full erase */
249 if (dip_switch != 0) {
250 /* start bootloader */
251 puts("DIP: Enabled\n");
252 env_set("actual_bank", "0");
256 #if defined(CONFIG_KM_FPGA_CONFIG)
257 wait_for_fpga_config();
259 toggle_eeprom_spi_bus();
264 static const u32 spi_mpp_config[] = {
271 static u32 spi_mpp_backup[4];
273 int mvebu_board_spi_claim_bus(struct udevice *dev)
275 spi_mpp_backup[3] = 0;
277 /* set new spi mpp config and save current one */
278 kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
280 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
285 int mvebu_board_spi_release_bus(struct udevice *dev)
287 /* restore saved mpp config */
288 kirkwood_mpp_conf(spi_mpp_backup, NULL);
290 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
295 #if (defined(CONFIG_KM_PIGGY4_88E6061))
297 #define PHY_LED_SEL_REG 0x18
298 #define PHY_LED0_LINK (0x5)
299 #define PHY_LED1_ACT (0x8<<4)
300 #define PHY_LED2_INT (0xe<<8)
301 #define PHY_SPEC_CTRL_REG 0x1c
302 #define PHY_RGMII_CLK_STABLE (0x1<<10)
303 #define PHY_CLSA (0x1<<1)
305 /* Configure and enable MV88E3018 PHY */
308 char *name = "egiga0";
311 if (miiphy_set_current_dev(name))
314 /* RGMII clk transition on data stable */
315 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
316 printf("Error reading PHY spec ctrl reg\n");
317 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
318 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
319 printf("Error writing PHY spec ctrl reg\n");
322 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
323 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
324 printf("Error writing PHY LED reg\n");
327 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
329 #elif defined(CONFIG_KM_PIGGY4_88E6352)
331 #include <mv88e6352.h>
333 #if defined(CONFIG_KM_NUSA)
334 struct mv88e_sw_reg extsw_conf[] = {
336 * port 0, PIGGY4, autoneg
337 * first the fix for the 1000Mbits Autoneg, this is from
338 * a Marvell errata, the regs are undocumented
340 { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
341 { PHY(0), PHY_STATUS, AN1000FIX },
342 { PHY(0), PHY_PAGE, 0 },
343 /* now the real port and phy configuration */
344 { PORT(0), PORT_PHY, NO_SPEED_FOR },
345 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
346 { PHY(0), PHY_1000_CTRL, NO_ADV },
347 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
348 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
351 { PORT(1), PORT_CTRL, PORT_DIS },
352 { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
353 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
355 { PORT(2), PORT_CTRL, PORT_DIS },
356 { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
357 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
359 { PORT(3), PORT_CTRL, PORT_DIS },
360 { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
361 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
362 /* port 4, ICNEV, SerDes, SGMII */
363 { PORT(4), PORT_STATUS, NO_PHY_DETECT },
364 { PORT(4), PORT_PHY, SPEED_1000_FOR },
365 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
366 { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
367 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
368 /* port 5, CPU_RGMII */
369 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
370 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
371 FULL_DPX_FOR | SPEED_1000_FOR },
372 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
373 /* port 6, unused, this port has no phy */
374 { PORT(6), PORT_CTRL, PORT_DIS },
377 struct mv88e_sw_reg extsw_conf[] = {};
382 #if defined(CONFIG_KM_MVEXTSW_ADDR)
383 char *name = "egiga0";
385 if (miiphy_set_current_dev(name))
388 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
389 ARRAY_SIZE(extsw_conf));
390 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
395 /* Configure and enable MV88E1118 PHY on the piggy*/
399 unsigned char model, rev;
401 char *name = "egiga0";
403 if (miiphy_set_current_dev(name))
407 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
410 if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
413 /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
414 if ((oui == PHY_MARVELL_OUI) &&
415 (model == PHY_MARVELL_88E1118R_MODEL)) {
416 /* set page register to 3 */
417 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
418 PHY_MARVELL_PAGE_REG,
419 PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
420 printf("Error writing PHY page reg\n");
423 * leds setup as printed on PCB:
424 * LED2 (Link): 0x0 (On Link, Off No Link)
425 * LED1 (Activity): 0x3 (On Activity, Off No Activity)
426 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
428 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
429 PHY_MARVELL_88E1118R_LED_CTRL_REG,
430 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
431 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
432 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
433 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
434 printf("Error writing PHY LED reg\n");
436 /* set page register back to 0 */
437 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
438 PHY_MARVELL_PAGE_REG,
439 PHY_MARVELL_DEFAULT_PAGE))
440 printf("Error writing PHY page reg\n");
446 #if defined(CONFIG_HUSH_INIT_VAR)
447 int hush_init_var(void)
449 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
454 #if defined(CONFIG_SYS_I2C_SOFT)
455 void set_sda(int state)
461 void set_scl(int state)
474 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
478 #if defined(CONFIG_POST)
480 #define KM_POST_EN_L 44
481 #define POST_WORD_OFF 8
483 int post_hotkeys_pressed(void)
485 #if defined(CONFIG_KM_COGE5UN)
486 return kw_gpio_get_value(KM_POST_EN_L);
488 return !kw_gpio_get_value(KM_POST_EN_L);
492 ulong post_word_load(void)
494 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
495 return in_le32(addr);
498 void post_word_store(ulong value)
500 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
501 out_le32(addr, value);
504 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
506 *vstart = CONFIG_SYS_SDRAM_BASE;
508 /* we go up to relocation plus a 1 MB margin */
509 *size = CONFIG_SYS_TEXT_BASE - (1<<20);
515 #if defined(CONFIG_SYS_EEPROM_WREN)
516 int eeprom_write_enable(unsigned dev_addr, int state)
518 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
520 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);