1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
12 * (C) Copyright 2008 - 2010
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
18 #include <fdt_support.h>
26 #include <asm/processor.h>
28 #include <linux/libfdt.h>
31 #include "../common/common.h"
33 DECLARE_GLOBAL_DATA_PTR;
35 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
37 const qe_iop_conf_t qe_iop_conf_tab[] = {
38 /* port pin dir open_drain assign */
39 #if defined(CONFIG_ARCH_MPC8360)
41 {0, 1, 3, 0, 2}, /* MDIO */
42 {0, 2, 1, 0, 1}, /* MDC */
45 {1, 14, 1, 0, 1}, /* TxD0 */
46 {1, 15, 1, 0, 1}, /* TxD1 */
47 {1, 20, 2, 0, 1}, /* RxD0 */
48 {1, 21, 2, 0, 1}, /* RxD1 */
49 {1, 18, 1, 0, 1}, /* TX_EN */
50 {1, 26, 2, 0, 1}, /* RX_DV */
51 {1, 27, 2, 0, 1}, /* RX_ER */
52 {1, 24, 2, 0, 1}, /* COL */
53 {1, 25, 2, 0, 1}, /* CRS */
54 {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
55 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
58 {5, 0, 1, 0, 2}, /* UART2_SOUT */
59 {5, 2, 1, 0, 1}, /* UART2_RTS */
60 {5, 3, 2, 0, 2}, /* UART2_SIN */
61 {5, 1, 2, 0, 3}, /* UART2_CTS */
62 #elif !defined(CONFIG_ARCH_MPC8309)
64 {0, 16, 1, 0, 3}, /* LA00 */
65 {0, 17, 1, 0, 3}, /* LA01 */
66 {0, 18, 1, 0, 3}, /* LA02 */
67 {0, 19, 1, 0, 3}, /* LA03 */
68 {0, 20, 1, 0, 3}, /* LA04 */
69 {0, 21, 1, 0, 3}, /* LA05 */
70 {0, 22, 1, 0, 3}, /* LA06 */
71 {0, 23, 1, 0, 3}, /* LA07 */
72 {0, 24, 1, 0, 3}, /* LA08 */
73 {0, 25, 1, 0, 3}, /* LA09 */
74 {0, 26, 1, 0, 3}, /* LA10 */
75 {0, 27, 1, 0, 3}, /* LA11 */
76 {0, 28, 1, 0, 3}, /* LA12 */
77 {0, 29, 1, 0, 3}, /* LA13 */
78 {0, 30, 1, 0, 3}, /* LA14 */
79 {0, 31, 1, 0, 3}, /* LA15 */
82 {3, 4, 3, 0, 2}, /* MDIO */
83 {3, 5, 1, 0, 2}, /* MDC */
86 {1, 18, 1, 0, 1}, /* TxD0 */
87 {1, 19, 1, 0, 1}, /* TxD1 */
88 {1, 22, 2, 0, 1}, /* RxD0 */
89 {1, 23, 2, 0, 1}, /* RxD1 */
90 {1, 26, 2, 0, 1}, /* RxER */
91 {1, 28, 2, 0, 1}, /* Rx_DV */
92 {1, 30, 1, 0, 1}, /* TxEN */
93 {1, 31, 2, 0, 1}, /* CRS */
94 {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
98 {0, 0, 0, 0, QE_IOP_TAB_END},
101 #if defined(CONFIG_SUVD3)
102 const uint upma_table[] = {
103 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
104 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
105 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
106 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
107 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
108 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
109 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
110 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
111 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
112 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
113 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
114 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
115 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
116 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
117 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
118 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
122 static int piggy_present(void)
124 struct km_bec_fpga __iomem *base =
125 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
127 return in_8(&base->bprth) & PIGGY_PRESENT;
130 int ethernet_present(void)
132 return piggy_present();
135 int board_early_init_r(void)
137 struct km_bec_fpga *base =
138 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
139 #if defined(CONFIG_SUVD3)
140 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
141 fsl_lbc_t *lbc = &immap->im_lbc;
142 u32 *mxmr = &lbc->mamr;
145 #if defined(CONFIG_ARCH_MPC8360)
148 * Because of errata in the UCCs, we have to write to the reserved
149 * registers to slow the clocks down.
151 svid = SVR_REV(mfspr(SVR));
155 * MPC8360ECE.pdf QE_ENET10 table 4:
156 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
157 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
159 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
163 * MPC8360ECE.pdf QE_ENET10 table 4:
164 * IMMR + 0x14AC[24:27] = 1010
166 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
167 0x00000050, 0x000000a0);
172 /* enable the PHY on the PIGGY */
173 setbits_8(&base->pgy_eth, 0x01);
174 /* enable the Unit LED (green) */
175 setbits_8(&base->oprth, WRL_BOOT);
176 /* enable Application Buffer */
177 setbits_8(&base->oprtl, OPRTL_XBUFENA);
179 #if defined(CONFIG_SUVD3)
180 /* configure UPMA for APP1 */
181 upmconfig(UPMA, (uint *) upma_table,
182 sizeof(upma_table) / sizeof(uint));
183 out_be32(mxmr, CONFIG_SYS_MAMR);
188 int misc_init_r(void)
190 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
191 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
195 int last_stage_init(void)
197 #if defined(CONFIG_TARGET_KMCOGE5NE)
198 struct bfticu_iomap *base =
199 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
200 u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
202 if (dip_switch != 0) {
203 /* start bootloader */
204 puts("DIP: Enabled\n");
205 env_set("actual_bank", "0");
212 static int fixed_sdram(void)
214 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
219 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
220 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
221 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
222 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
223 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
224 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
225 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
226 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
227 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
228 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
229 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
230 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
231 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
233 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
235 msize = CONFIG_SYS_DDR_SIZE << 20;
236 disable_addr_trans();
237 msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
239 msize /= (1024 * 1024);
240 if (CONFIG_SYS_DDR_SIZE != msize) {
241 for (ddr_size = msize << 20, ddr_size_log2 = 0;
243 ddr_size = ddr_size >> 1, ddr_size_log2++)
246 out_be32(&im->sysconf.ddrlaw[0].ar,
247 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
248 out_be32(&im->ddr.csbnds[0].csbnds,
249 (((msize / 16) - 1) & 0xff));
257 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
260 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
263 out_be32(&im->sysconf.ddrlaw[0].bar,
264 CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
265 msize = fixed_sdram();
267 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
269 * Initialize DDR ECC byte
271 ddr_enable_ecc(msize * 1024 * 1024);
274 /* return total bus SDRAM size(bytes) -- DDR */
275 gd->ram_size = msize * 1024 * 1024;
282 puts("Board: ABB " CONFIG_SYS_CONFIG_NAME);
285 puts(" with PIGGY.");
290 int ft_board_setup(void *blob, bd_t *bd)
292 ft_cpu_setup(blob, bd);
297 #if defined(CONFIG_HUSH_INIT_VAR)
298 int hush_init_var(void)
300 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
305 #if defined(CONFIG_POST)
306 int post_hotkeys_pressed(void)
309 struct km_bec_fpga *base =
310 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
311 int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
312 testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
313 debug("post_hotkeys_pressed: %d\n", !testpin);
317 ulong post_word_load(void)
319 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
320 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
321 return in_le32(addr);
324 void post_word_store(ulong value)
326 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
327 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
328 out_le32(addr, value);
331 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
334 * These match CONFIG_SYS_MEMTEST_START and
335 * (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START)
337 *vstart = 0x00100000;
339 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);