board/keymile/km83xx/km83xx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2008 - 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #include <common.h>
  17 #include <env.h>
  18 #include <fdt_support.h>
  19 #include <init.h>
  20 #include <ioports.h>
  21 #include <log.h>
  22 #include <mpc83xx.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <asm/global_data.h>
  26 #include <asm/io.h>
  27 #include <asm/mmu.h>
  28 #include <asm/processor.h>
  29 #include <pci.h>
  30 #include <linux/delay.h>
  31 #include <linux/libfdt.h>
  32 #include <post.h>
  33
  34 #include "../common/common.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #if CONFIG_IS_ENABLED(TARGET_KMCOGE5NE) || CONFIG_IS_ENABLED(TARGET_KMETER1)
  39 #define CFG_SYS_DDR_MODE        0x47860452
  40 #define CFG_SYS_DDR_INTERVAL (\
  41         (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  42         (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
  43 #define CFG_SYS_DDR_TIMING_0 (\
  44         (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  45         (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  46         (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  47         (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  48         (0 << TIMING_CFG0_WWT_SHIFT) | \
  49         (0 << TIMING_CFG0_RRT_SHIFT) | \
  50         (0 << TIMING_CFG0_WRT_SHIFT) | \
  51         (0 << TIMING_CFG0_RWT_SHIFT))
  52
  53 #define CFG_SYS_DDR_TIMING_1    ((TIMING_CFG1_CASLAT_50) | \
  54                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  55                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  56                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
  57                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
  58                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  59                                  (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  60                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
  61
  62 #define CFG_SYS_DDR_TIMING_2 (\
  63         (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
  64         (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
  65         (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
  66         (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
  67         (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
  68         (5 << TIMING_CFG2_CPO_SHIFT) | \
  69         (0 << TIMING_CFG2_ADD_LAT_SHIFT))
  70
  71 #define CFG_SYS_DDR_TIMING_3                    0x00000000
  72
  73 #else
  74 #define CFG_SYS_DDR_MODE        0x47860242
  75 #define CFG_SYS_DDR_INTERVAL    ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  76                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
  77
  78 #define CFG_SYS_DDR_TIMING_0    ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  79                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  80                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  81                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  82                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
  83                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
  84                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
  85                                  (0 << TIMING_CFG0_RWT_SHIFT))
  86
  87 #define CFG_SYS_DDR_TIMING_1    ((TIMING_CFG1_CASLAT_40) | \
  88                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  89                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  90                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
  91                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
  92                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  93                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  94                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
  95
  96 #define CFG_SYS_DDR_TIMING_2    ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
  97                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
  98                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
  99                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 100                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 101                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 102                                  (5 << TIMING_CFG2_CPO_SHIFT))
 103
 104 #define CFG_SYS_DDR_TIMING_3    0x00000000
 105
 106 #define CFG_SYS_DDR_CS0_CONFIG  (CSCONFIG_EN | CSCONFIG_AP | \
 107                                          CSCONFIG_ODT_WR_CFG | \
 108                                          CSCONFIG_ROW_BIT_13 | \
 109                                          CSCONFIG_COL_BIT_10)
 110 #endif
 111
 112 #define CFG_SYS_DDR_SDRAM_CFG   (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 113                                          SDRAM_CFG_32_BE | \
 114                                          SDRAM_CFG_SREN | \
 115                                          SDRAM_CFG_HSE)
 116 #define CFG_SYS_DDR_CLK_CNTL            (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 117 #define CFG_SYS_DDR_SDRAM_CFG2  0x00401000
 118 #define CFG_SYS_DDR_CS0_BNDS    0x0000007f
 119 #define CFG_SYS_DDR_MODE2       0x8080c000
 120
 121 #define CFG_SYS_SDRAM_SIZE      0x80000000 /* 2048 MiB */
 122
 123 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 124
 125 static int piggy_present(void)
 126 {
 127         struct km_bec_fpga __iomem *base =
 128                 (struct km_bec_fpga __iomem *)CFG_SYS_KMBEC_FPGA_BASE;
 129
 130         return in_8(&base->bprth) & PIGGY_PRESENT;
 131 }
 132
 133 int ethernet_present(void)
 134 {
 135         return piggy_present();
 136 }
 137
 138 int board_early_init_r(void)
 139 {
 140         struct km_bec_fpga *base =
 141                 (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
 142
 143 #if defined(CONFIG_ARCH_MPC8360)
 144         unsigned short  svid;
 145         /*
 146          * Because of errata in the UCCs, we have to write to the reserved
 147          * registers to slow the clocks down.
 148          */
 149         svid =  SVR_REV(mfspr(SVR));
 150         switch (svid) {
 151         case 0x0020:
 152                 /*
 153                  * MPC8360ECE.pdf QE_ENET10 table 4:
 154                  * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
 155                  * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
 156                  */
 157                 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
 158                 break;
 159         case 0x0021:
 160                 /*
 161                  * MPC8360ECE.pdf QE_ENET10 table 4:
 162                  * IMMR + 0x14AC[24:27] = 1010
 163                  */
 164                 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
 165                         0x00000050, 0x000000a0);
 166                 break;
 167         }
 168 #endif
 169
 170         /* enable the PHY on the PIGGY */
 171         setbits_8(&base->pgy_eth, 0x01);
 172         /* enable the Unit LED (green) */
 173         setbits_8(&base->oprth, WRL_BOOT);
 174         /* enable Application Buffer */
 175         setbits_8(&base->oprtl, OPRTL_XBUFENA);
 176
 177         return 0;
 178 }
 179
 180 int misc_init_r(void)
 181 {
 182         ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
 183                         CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
 184         return 0;
 185 }
 186
 187 int last_stage_init(void)
 188 {
 189 #if defined(CONFIG_TARGET_KMCOGE5NE)
 190         /*
 191          * BFTIC3 on the local bus CS4
 192          */
 193         struct bfticu_iomap *base = (struct bfticu_iomap *)0xB0000000;
 194         u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
 195
 196         if (dip_switch != 0) {
 197                 /* start bootloader */
 198                 puts("DIP:   Enabled\n");
 199                 env_set("actual_bank", "0");
 200         }
 201 #endif
 202         set_km_env();
 203         return 0;
 204 }
 205
 206 static int fixed_sdram(void)
 207 {
 208         immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 209         u32 msize = 0;
 210         u32 ddr_size;
 211         u32 ddr_size_log2;
 212
 213         out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
 214         out_be32(&im->ddr.csbnds[0].csbnds, (CFG_SYS_DDR_CS0_BNDS) | 0x7f);
 215         out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
 216         out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
 217         out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
 218         out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
 219         out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
 220         out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
 221         out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2);
 222         out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE);
 223         out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2);
 224         out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL);
 225         out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL);
 226         udelay(200);
 227         setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
 228
 229         disable_addr_trans();
 230         msize = get_ram_size(CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
 231         enable_addr_trans();
 232         msize /= (1024 * 1024);
 233         if (CFG_SYS_SDRAM_SIZE >> 20 != msize) {
 234                 for (ddr_size = msize << 20, ddr_size_log2 = 0;
 235                         (ddr_size > 1);
 236                         ddr_size = ddr_size >> 1, ddr_size_log2++)
 237                         if (ddr_size & 1)
 238                                 return -1;
 239                 out_be32(&im->sysconf.ddrlaw[0].ar,
 240                         (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
 241                 out_be32(&im->ddr.csbnds[0].csbnds,
 242                         (((msize / 16) - 1) & 0xff));
 243         }
 244
 245         return msize;
 246 }
 247
 248 int dram_init(void)
 249 {
 250         immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 251         u32 msize = 0;
 252
 253         if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
 254                 return -ENXIO;
 255
 256         out_be32(&im->sysconf.ddrlaw[0].bar,
 257                 CFG_SYS_SDRAM_BASE & LAWBAR_BAR);
 258         msize = fixed_sdram();
 259
 260 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 261         /*
 262          * Initialize DDR ECC byte
 263          */
 264         ddr_enable_ecc(msize * 1024 * 1024);
 265 #endif
 266
 267         /* return total bus SDRAM size(bytes)  -- DDR */
 268         gd->ram_size = msize * 1024 * 1024;
 269
 270         return 0;
 271 }
 272
 273 int checkboard(void)
 274 {
 275         puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME);
 276
 277         if (piggy_present())
 278                 puts(" with PIGGY.");
 279         puts("\n");
 280         return 0;
 281 }
 282
 283 int ft_board_setup(void *blob, struct bd_info *bd)
 284 {
 285         ft_cpu_setup(blob, bd);
 286
 287         return 0;
 288 }
 289
 290 #if defined(CONFIG_HUSH_INIT_VAR)
 291 int hush_init_var(void)
 292 {
 293         ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
 294         return 0;
 295 }
 296 #endif
 297
 298 #if defined(CONFIG_POST)
 299 int post_hotkeys_pressed(void)
 300 {
 301         int testpin = 0;
 302         struct km_bec_fpga *base =
 303                 (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
 304         int testpin_reg = in_8(&base->CFG_TESTPIN_REG);
 305         testpin = (testpin_reg & CFG_TESTPIN_MASK) != 0;
 306         debug("post_hotkeys_pressed: %d\n", !testpin);
 307         return testpin;
 308 }
 309
 310 ulong post_word_load(void)
 311 {
 312         void* addr = (ulong *) (CPM_POST_WORD_ADDR);
 313         debug("post_word_load 0x%08lX:  0x%08X\n", (ulong)addr, in_le32(addr));
 314         return in_le32(addr);
 315
 316 }
 317 void post_word_store(ulong value)
 318 {
 319         void* addr = (ulong *) (CPM_POST_WORD_ADDR);
 320         debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
 321         out_le32(addr, value);
 322 }
 323
 324 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 325 {
 326         *vstart = CONFIG_SYS_MEMTEST_START;
 327         *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
 328         debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
 329
 330         return 0;
 331 }
 332 #endif