1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
12 * (C) Copyright 2008 - 2010
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
18 #include <fdt_support.h>
25 #include <asm/global_data.h>
28 #include <asm/processor.h>
30 #include <linux/delay.h>
31 #include <linux/libfdt.h>
34 #include "../common/common.h"
36 DECLARE_GLOBAL_DATA_PTR;
38 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
40 static int piggy_present(void)
42 struct km_bec_fpga __iomem *base =
43 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
45 return in_8(&base->bprth) & PIGGY_PRESENT;
48 int ethernet_present(void)
50 return piggy_present();
53 int board_early_init_r(void)
55 struct km_bec_fpga *base =
56 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
58 #if defined(CONFIG_ARCH_MPC8360)
61 * Because of errata in the UCCs, we have to write to the reserved
62 * registers to slow the clocks down.
64 svid = SVR_REV(mfspr(SVR));
68 * MPC8360ECE.pdf QE_ENET10 table 4:
69 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
70 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
72 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
76 * MPC8360ECE.pdf QE_ENET10 table 4:
77 * IMMR + 0x14AC[24:27] = 1010
79 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
80 0x00000050, 0x000000a0);
85 /* enable the PHY on the PIGGY */
86 setbits_8(&base->pgy_eth, 0x01);
87 /* enable the Unit LED (green) */
88 setbits_8(&base->oprth, WRL_BOOT);
89 /* enable Application Buffer */
90 setbits_8(&base->oprtl, OPRTL_XBUFENA);
97 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
98 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
102 int last_stage_init(void)
104 #if defined(CONFIG_TARGET_KMCOGE5NE)
106 * BFTIC3 on the local bus CS4
108 struct bfticu_iomap *base = (struct bfticu_iomap *)0xB0000000;
109 u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
111 if (dip_switch != 0) {
112 /* start bootloader */
113 puts("DIP: Enabled\n");
114 env_set("actual_bank", "0");
121 static int fixed_sdram(void)
123 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
128 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
129 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
130 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
131 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
132 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
133 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
134 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
135 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
136 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
137 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
138 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
139 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
140 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
142 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
144 disable_addr_trans();
145 msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
147 msize /= (1024 * 1024);
148 if (CONFIG_SYS_SDRAM_SIZE >> 20 != msize) {
149 for (ddr_size = msize << 20, ddr_size_log2 = 0;
151 ddr_size = ddr_size >> 1, ddr_size_log2++)
154 out_be32(&im->sysconf.ddrlaw[0].ar,
155 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
156 out_be32(&im->ddr.csbnds[0].csbnds,
157 (((msize / 16) - 1) & 0xff));
165 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
168 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
171 out_be32(&im->sysconf.ddrlaw[0].bar,
172 CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
173 msize = fixed_sdram();
175 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
177 * Initialize DDR ECC byte
179 ddr_enable_ecc(msize * 1024 * 1024);
182 /* return total bus SDRAM size(bytes) -- DDR */
183 gd->ram_size = msize * 1024 * 1024;
190 puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME);
193 puts(" with PIGGY.");
198 int ft_board_setup(void *blob, struct bd_info *bd)
200 ft_cpu_setup(blob, bd);
205 #if defined(CONFIG_HUSH_INIT_VAR)
206 int hush_init_var(void)
208 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
213 #if defined(CONFIG_POST)
214 int post_hotkeys_pressed(void)
217 struct km_bec_fpga *base =
218 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
219 int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
220 testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
221 debug("post_hotkeys_pressed: %d\n", !testpin);
225 ulong post_word_load(void)
227 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
228 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
229 return in_le32(addr);
232 void post_word_store(ulong value)
234 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
235 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
236 out_le32(addr, value);
239 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
241 *vstart = CONFIG_SYS_MEMTEST_START;
242 *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
243 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);