1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
12 * (C) Copyright 2008 - 2010
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
18 #include <fdt_support.h>
27 #include <asm/processor.h>
29 #include <linux/delay.h>
30 #include <linux/libfdt.h>
33 #include "../common/common.h"
35 DECLARE_GLOBAL_DATA_PTR;
37 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
39 static int piggy_present(void)
41 struct km_bec_fpga __iomem *base =
42 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
44 return in_8(&base->bprth) & PIGGY_PRESENT;
47 int ethernet_present(void)
49 return piggy_present();
52 int board_early_init_r(void)
54 struct km_bec_fpga *base =
55 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
57 #if defined(CONFIG_ARCH_MPC8360)
60 * Because of errata in the UCCs, we have to write to the reserved
61 * registers to slow the clocks down.
63 svid = SVR_REV(mfspr(SVR));
67 * MPC8360ECE.pdf QE_ENET10 table 4:
68 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
69 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
71 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
75 * MPC8360ECE.pdf QE_ENET10 table 4:
76 * IMMR + 0x14AC[24:27] = 1010
78 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
79 0x00000050, 0x000000a0);
84 /* enable the PHY on the PIGGY */
85 setbits_8(&base->pgy_eth, 0x01);
86 /* enable the Unit LED (green) */
87 setbits_8(&base->oprth, WRL_BOOT);
88 /* enable Application Buffer */
89 setbits_8(&base->oprtl, OPRTL_XBUFENA);
96 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
97 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
101 int last_stage_init(void)
103 #if defined(CONFIG_TARGET_KMCOGE5NE)
104 struct bfticu_iomap *base =
105 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
106 u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
108 if (dip_switch != 0) {
109 /* start bootloader */
110 puts("DIP: Enabled\n");
111 env_set("actual_bank", "0");
118 static int fixed_sdram(void)
120 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
125 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
126 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
127 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
128 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
129 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
130 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
131 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
132 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
133 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
134 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
135 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
136 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
137 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
139 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
141 msize = CONFIG_SYS_DDR_SIZE << 20;
142 disable_addr_trans();
143 msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
145 msize /= (1024 * 1024);
146 if (CONFIG_SYS_DDR_SIZE != msize) {
147 for (ddr_size = msize << 20, ddr_size_log2 = 0;
149 ddr_size = ddr_size >> 1, ddr_size_log2++)
152 out_be32(&im->sysconf.ddrlaw[0].ar,
153 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
154 out_be32(&im->ddr.csbnds[0].csbnds,
155 (((msize / 16) - 1) & 0xff));
163 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
166 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
169 out_be32(&im->sysconf.ddrlaw[0].bar,
170 CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
171 msize = fixed_sdram();
173 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
175 * Initialize DDR ECC byte
177 ddr_enable_ecc(msize * 1024 * 1024);
180 /* return total bus SDRAM size(bytes) -- DDR */
181 gd->ram_size = msize * 1024 * 1024;
188 puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME);
191 puts(" with PIGGY.");
196 int ft_board_setup(void *blob, struct bd_info *bd)
198 ft_cpu_setup(blob, bd);
203 #if defined(CONFIG_HUSH_INIT_VAR)
204 int hush_init_var(void)
206 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
211 #if defined(CONFIG_POST)
212 int post_hotkeys_pressed(void)
215 struct km_bec_fpga *base =
216 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
217 int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
218 testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
219 debug("post_hotkeys_pressed: %d\n", !testpin);
223 ulong post_word_load(void)
225 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
226 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
227 return in_le32(addr);
230 void post_word_store(ulong value)
232 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
233 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
234 out_le32(addr, value);
237 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
240 * These match CONFIG_SYS_MEMTEST_START and
241 * (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START)
243 *vstart = 0x00100000;
245 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);