2 * (C) Copyright 2007 - 2008
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
14 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
19 #include "../common/common.h"
21 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
24 * I/O Port configuration table
26 * if conf is 1, then that port pin will be configured at boot time
27 * according to the five values podr/pdir/ppar/psor/pdat for that entry
29 const iop_conf_t iop_conf_tab[4][32] = {
32 { /* conf ppar psor pdir podr pdat */
33 { 0, 0, 0, 0, 0, 0 }, /* PA31 */
34 { 0, 0, 0, 0, 0, 0 }, /* PA30 */
35 { 0, 0, 0, 0, 0, 0 }, /* PA29 */
36 { 0, 0, 0, 0, 0, 0 }, /* PA28 */
37 { 0, 0, 0, 0, 0, 0 }, /* PA27 */
38 { 0, 0, 0, 0, 0, 0 }, /* PA26 */
39 { 0, 0, 0, 0, 0, 0 }, /* PA25 */
40 { 0, 0, 0, 0, 0, 0 }, /* PA24 */
41 { 0, 0, 0, 0, 0, 0 }, /* PA23 */
42 { 0, 0, 0, 0, 0, 0 }, /* PA22 */
43 { 0, 0, 0, 0, 0, 0 }, /* PA21 */
44 { 0, 0, 0, 0, 0, 0 }, /* PA20 */
45 { 0, 0, 0, 0, 0, 0 }, /* PA19 */
46 { 0, 0, 0, 0, 0, 0 }, /* PA18 */
47 { 0, 0, 0, 0, 0, 0 }, /* PA17 */
48 { 0, 0, 0, 0, 0, 0 }, /* PA16 */
49 { 0, 0, 0, 0, 0, 0 }, /* PA15 */
50 { 0, 0, 0, 0, 0, 0 }, /* PA14 */
51 { 0, 0, 0, 0, 0, 0 }, /* PA13 */
52 { 0, 0, 0, 0, 0, 0 }, /* PA12 */
53 { 0, 0, 0, 0, 0, 0 }, /* PA11 */
54 { 0, 0, 0, 0, 0, 0 }, /* PA10 */
55 { 1, 1, 0, 1, 0, 0 }, /* PA9 SMC2 TxD */
56 { 1, 1, 0, 0, 0, 0 }, /* PA8 SMC2 RxD */
57 { 0, 0, 0, 0, 0, 0 }, /* PA7 */
58 { 0, 0, 0, 0, 0, 0 }, /* PA6 */
59 { 0, 0, 0, 0, 0, 0 }, /* PA5 */
60 { 0, 0, 0, 0, 0, 0 }, /* PA4 */
61 { 0, 0, 0, 0, 0, 0 }, /* PA3 */
62 { 0, 0, 0, 0, 0, 0 }, /* PA2 */
63 { 0, 0, 0, 0, 0, 0 }, /* PA1 */
64 { 0, 0, 0, 0, 0, 0 } /* PA0 */
68 { /* conf ppar psor pdir podr pdat */
69 { 0, 0, 0, 0, 0, 0 }, /* PB31 */
70 { 0, 0, 0, 0, 0, 0 }, /* PB30 */
71 { 0, 0, 0, 0, 0, 0 }, /* PB29 */
72 { 0, 0, 0, 0, 0, 0 }, /* PB28 */
73 { 0, 0, 0, 0, 0, 0 }, /* PB27 */
74 { 0, 0, 0, 0, 0, 0 }, /* PB26 */
75 { 0, 0, 0, 0, 0, 0 }, /* PB25 */
76 { 0, 0, 0, 0, 0, 0 }, /* PB24 */
77 { 0, 0, 0, 0, 0, 0 }, /* PB23 */
78 { 0, 0, 0, 0, 0, 0 }, /* PB22 */
79 { 0, 0, 0, 0, 0, 0 }, /* PB21 */
80 { 0, 0, 0, 0, 0, 0 }, /* PB20 */
81 { 0, 0, 0, 0, 0, 0 }, /* PB19 */
82 { 0, 0, 0, 0, 0, 0 }, /* PB18 */
83 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
84 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
85 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
86 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
87 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
88 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
89 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
90 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
91 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
92 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
93 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
94 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
95 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
96 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
97 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
98 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
99 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
100 { 0, 0, 0, 0, 0, 0 } /* non-existent */
104 { /* conf ppar psor pdir podr pdat */
105 { 0, 0, 0, 0, 0, 0 }, /* PC31 */
106 { 0, 0, 0, 0, 0, 0 }, /* PC30 */
107 { 0, 0, 0, 0, 0, 0 }, /* PC29 */
108 { 0, 0, 0, 0, 0, 0 }, /* PC28 */
109 { 0, 0, 0, 0, 0, 0 }, /* PC27 */
110 { 0, 0, 0, 0, 0, 0 }, /* PC26 */
111 { 1, 1, 0, 0, 0, 0 }, /* PC25 RxClk */
112 { 1, 1, 0, 0, 0, 0 }, /* PC24 TxClk */
113 { 0, 0, 0, 0, 0, 0 }, /* PC23 */
114 { 0, 0, 0, 0, 0, 0 }, /* PC22 */
115 { 0, 0, 0, 0, 0, 0 }, /* PC21 */
116 { 0, 0, 0, 0, 0, 0 }, /* PC20 */
117 { 0, 0, 0, 0, 0, 0 }, /* PC19 */
118 { 0, 0, 0, 0, 0, 0 }, /* PC18 */
119 { 0, 0, 0, 0, 0, 0 }, /* PC17 */
120 { 0, 0, 0, 0, 0, 0 }, /* PC16 */
121 { 0, 0, 0, 0, 0, 0 }, /* PC15 */
122 { 0, 0, 0, 0, 0, 0 }, /* PC14 */
123 { 0, 0, 0, 0, 0, 0 }, /* PC13 */
124 { 0, 0, 0, 0, 0, 0 }, /* PC12 */
125 { 0, 0, 0, 0, 0, 0 }, /* PC11 */
126 { 0, 0, 0, 0, 0, 0 }, /* PC10 */
127 { 1, 1, 0, 0, 0, 0 }, /* PC9 SCC4: CTS */
128 { 1, 1, 0, 0, 0, 0 }, /* PC8 SCC4: CD */
129 { 0, 0, 0, 0, 0, 0 }, /* PC7 */
130 { 0, 0, 0, 0, 0, 0 }, /* PC6 */
131 { 0, 0, 0, 0, 0, 0 }, /* PC5 */
132 { 0, 0, 0, 0, 0, 0 }, /* PC4 */
133 { 0, 0, 0, 0, 0, 0 }, /* PC3 */
134 { 0, 0, 0, 0, 0, 0 }, /* PC2 */
135 { 0, 0, 0, 0, 0, 0 }, /* PC1 */
136 { 0, 0, 0, 0, 0, 0 }, /* PC0 */
140 { /* conf ppar psor pdir podr pdat */
141 { 0, 0, 0, 0, 0, 0 }, /* PD31 */
142 { 0, 0, 0, 0, 0, 0 }, /* PD30 */
143 { 0, 0, 0, 0, 0, 0 }, /* PD29 */
144 { 0, 0, 0, 0, 0, 0 }, /* PD28 */
145 { 0, 0, 0, 0, 0, 0 }, /* PD27 */
146 { 0, 0, 0, 0, 0, 0 }, /* PD26 */
147 { 0, 0, 0, 0, 0, 0 }, /* PD25 */
148 { 0, 0, 0, 0, 0, 0 }, /* PD24 */
149 { 0, 0, 0, 0, 0, 0 }, /* PD23 */
150 { 1, 1, 0, 0, 0, 0 }, /* PD22 SCC4: RXD */
151 { 1, 1, 0, 1, 0, 0 }, /* PD21 SCC4: TXD */
152 { 1, 1, 0, 1, 0, 0 }, /* PD20 SCC4: RTS */
153 { 0, 0, 0, 0, 0, 0 }, /* PD19 */
154 { 0, 0, 0, 0, 0, 0 }, /* PD18 */
155 { 0, 0, 0, 0, 0, 0 }, /* PD17 */
156 { 0, 0, 0, 0, 0, 0 }, /* PD16 */
157 #if defined(CONFIG_HARD_I2C)
158 { 1, 1, 1, 0, 1, 0 }, /* PD15 I2C SDA */
159 { 1, 1, 1, 0, 1, 0 }, /* PD14 I2C SCL */
161 { 1, 0, 0, 0, 1, 1 }, /* PD15 */
162 { 1, 0, 0, 1, 1, 1 }, /* PD14 */
164 { 0, 0, 0, 0, 0, 0 }, /* PD13 */
165 { 0, 0, 0, 0, 0, 0 }, /* PD12 */
166 { 0, 0, 0, 0, 0, 0 }, /* PD11 */
167 { 0, 0, 0, 0, 0, 0 }, /* PD10 */
168 { 0, 0, 0, 0, 0, 0 }, /* PD9 */
169 { 0, 0, 0, 0, 0, 0 }, /* PD8 */
170 { 0, 0, 0, 0, 0, 0 }, /* PD7 */
171 { 0, 0, 0, 0, 0, 0 }, /* PD6 */
172 { 0, 0, 0, 0, 0, 0 }, /* PD5 */
173 { 0, 0, 0, 0, 0, 0 }, /* PD4 */
174 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
175 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
176 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
177 { 0, 0, 0, 0, 0, 0 } /* non-existent */
182 * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
184 * This routine performs standard 8260 initialization sequence
185 * and calculates the available memory size. It may be called
186 * several times to try different SDRAM configurations on both
187 * 60x and local buses.
189 static long int try_init(memctl8260_t *memctl, ulong sdmr,
190 ulong orx, uchar *base)
197 * We must be able to test a location outsize the maximum legal size
198 * to find out THAT we are outside; but this address still has to be
199 * mapped by the controller. That means, that the initial mapping has
200 * to be (at least) twice as large as the maximum expected size.
202 maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
204 out_be32(&memctl->memc_or1, orx);
207 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
209 * "At system reset, initialization software must set up the
210 * programmable parameters in the memory controller banks registers
211 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
212 * system software should execute the following initialization sequence
213 * for each SDRAM device.
215 * 1. Issue a PRECHARGE-ALL-BANKS command
216 * 2. Issue eight CBR REFRESH commands
217 * 3. Issue a MODE-SET command to initialize the mode register
219 * The initial commands are executed by setting P/LSDMR[OP] and
220 * accessing the SDRAM with a single-byte transaction."
222 * The appropriate BRx/ORx registers have already been set when we
223 * get here. The SDRAM can be accessed at the address
224 * CONFIG_SYS_SDRAM_BASE.
227 out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
230 out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
231 for (i = 0; i < 8; i++)
234 out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
235 /* setting MR on address lines */
236 out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
238 out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
241 size = get_ram_size((long *)base, maxsize);
242 out_be32(&memctl->memc_or1, orx | ~(size - 1));
247 #ifdef CONFIG_SYS_SDRAM_LIST
250 * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM
251 * configurations therein (should be from high to lower) to find the
252 * one actually matching the current configuration.
253 * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are
254 * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST
255 * (defined as the initialization value for the array of struct sdram_conf_s)
256 * will then be ORed with such base values.
259 struct sdram_conf_s {
265 static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST;
267 static long probe_sdram(memctl8260_t *memctl)
272 for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) {
273 psize = try_init(memctl,
274 CONFIG_SYS_PSDMR | sdram_conf[n].psdmr,
275 CONFIG_SYS_OR1 | sdram_conf[n].or1,
276 (uchar *) CONFIG_SYS_SDRAM_BASE);
277 debug("Probing %ld bytes returned %ld\n",
278 sdram_conf[n].size, psize);
279 if (psize == sdram_conf[n].size)
285 #else /* CONFIG_SYS_SDRAM_LIST */
287 static long probe_sdram(memctl8260_t *memctl)
289 return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
290 (uchar *) CONFIG_SYS_SDRAM_BASE);
292 #endif /* CONFIG_SYS_SDRAM_LIST */
295 phys_size_t initdram(int board_type)
297 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
298 memctl8260_t *memctl = &immap->im_memctl;
302 out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
303 out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
307 psize = probe_sdram(memctl);
316 #if defined(CONFIG_MGCOGE)
317 puts("Board: Keymile mgcoge");
319 puts("Board: Keymile mgcoge3ne");
321 if (ethernet_present())
322 puts(" with PIGGY.");
327 int last_stage_init(void)
329 struct bfticu_iomap *base =
330 (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE;
333 dip_switch = in_8(&base->mswitch);
334 dip_switch &= BFTICU_DIPSWITCH_MASK;
335 /* dip switch 'full reset' or 'db erase' */
336 if (dip_switch & 0x1 || dip_switch & 0x2) {
337 /* start bootloader */
338 puts("DIP: Enabled\n");
339 setenv("actual_bank", "0");
345 #ifdef CONFIG_MGCOGE3NE
346 static void set_pin(int state, unsigned long mask);
349 * For mgcoge3ne boards, the mgcoge3un control is controlled from
350 * a GPIO line on the PPC CPU. If bobcatreset is set the line
351 * will toggle once what forces the mgocge3un part to restart
354 static void handle_mgcoge3un_reset(void)
356 char *bobcatreset = getenv("bobcatreset");
358 if (strcmp(bobcatreset, "true") == 0) {
359 puts("Forcing bobcat reset\n");
360 set_pin(0, 0x00000004); /* clear PD29 to reset arm */
362 set_pin(1, 0x00000004);
364 set_pin(1, 0x00000004); /* set PD29 to not reset arm */
369 int ethernet_present(void)
371 struct km_bec_fpga *base =
372 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
374 return in_8(&base->bprth) & PIGGY_PRESENT;
378 * Early board initalization.
380 int board_early_init_r(void)
382 struct km_bec_fpga *base =
383 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
385 /* setup the UPIOx */
386 /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
387 out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
388 /* SCC4 enable, halfduplex, FCC1 powerdown */
389 out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
390 H_OPORTS_FCC1_PW_DWN));
392 #ifdef CONFIG_MGCOGE3NE
393 handle_mgcoge3un_reset();
398 int misc_init_r(void)
400 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
404 int hush_init_var(void)
406 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
410 #define SDA_MASK 0x00010000
411 #define SCL_MASK 0x00020000
413 static void set_pin(int state, unsigned long mask)
415 ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
418 setbits_be32(&iop->pdat, mask);
420 clrbits_be32(&iop->pdat, mask);
422 setbits_be32(&iop->pdir, mask);
425 static int get_pin(unsigned long mask)
427 ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
429 clrbits_be32(&iop->pdir, mask);
430 return 0 != (in_be32(&iop->pdat) & mask);
433 void set_sda(int state)
435 set_pin(state, SDA_MASK);
438 void set_scl(int state)
440 set_pin(state, SCL_MASK);
445 return get_pin(SDA_MASK);
450 return get_pin(SCL_MASK);
453 #if defined(CONFIG_HARD_I2C)
454 static void setports(int gpio)
456 ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
459 clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
460 clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
462 setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
463 clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
464 setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
468 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
469 int ft_board_setup(void *blob, bd_t *bd)
471 ft_cpu_setup(blob, bd);
475 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */