1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 Keymile AG
4 * Valentin Longchamp <valentin.longchamp@keymile.com>
8 #include <linux/bitops.h>
13 /* QRIO GPIO register offsets */
14 #define DIRECT_OFF 0x18
17 int qrio_get_gpio(u8 port_off, u8 gpio_nr)
21 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
23 gprt = in_be32(qrio_base + port_off + GPRT_OFF);
25 return (gprt >> gpio_nr) & 1U;
28 void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value)
32 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
36 gprt = in_be32(qrio_base + port_off + GPRT_OFF);
42 out_be32(qrio_base + port_off + GPRT_OFF, gprt);
45 void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value)
49 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
53 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
55 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
57 qrio_set_gpio(port_off, gpio_nr, value);
60 void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr)
64 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
68 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
70 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
73 void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
77 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
81 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
83 /* set to output -> GPIO drives low */
86 /* set to input -> GPIO floating */
89 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
92 #define WDMASK_OFF 0x16
94 void qrio_wdmask(u8 bit, bool wden)
97 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
99 wdmask = in_be16(qrio_base + WDMASK_OFF);
102 wdmask |= (1 << bit);
104 wdmask &= ~(1 << bit);
106 out_be16(qrio_base + WDMASK_OFF, wdmask);
109 #define PRST_OFF 0x1a
111 void qrio_prst(u8 bit, bool en, bool wden)
114 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
116 qrio_wdmask(bit, wden);
118 prst = in_be16(qrio_base + PRST_OFF);
125 out_be16(qrio_base + PRST_OFF, prst);
128 #define PRSTCFG_OFF 0x1c
130 void qrio_prstcfg(u8 bit, u8 mode)
134 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
136 prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
138 for (i = 0; i < 2; i++) {
140 set_bit(2 * bit + i, &prstcfg);
142 clear_bit(2 * bit + i, &prstcfg);
145 out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
148 #define CTRLH_OFF 0x02
149 #define CTRLH_WRL_BOOT 0x01
150 #define CTRLH_WRL_UNITRUN 0x02
152 void qrio_set_leds(void)
155 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
157 /* set UNIT LED to RED and BOOT LED to ON */
158 ctrlh = in_8(qrio_base + CTRLH_OFF);
159 ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN);
160 out_8(qrio_base + CTRLH_OFF, ctrlh);
163 #define CTRLL_OFF 0x03
164 #define CTRLL_WRB_BUFENA 0x20
166 void qrio_enable_app_buffer(void)
169 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
171 /* enable application buffer */
172 ctrll = in_8(qrio_base + CTRLL_OFF);
173 ctrll |= (CTRLL_WRB_BUFENA);
174 out_8(qrio_base + CTRLL_OFF, ctrll);
177 #define REASON1_OFF 0x12
178 #define REASON1_CPUWD 0x01
180 void qrio_cpuwd_flag(bool flag)
183 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
185 reason1 = in_8(qrio_base + REASON1_OFF);
187 reason1 |= REASON1_CPUWD;
189 reason1 &= ~REASON1_CPUWD;
190 out_8(qrio_base + REASON1_OFF, reason1);
193 #define REASON0_OFF 0x13
194 #define REASON0_SWURST 0x80
195 #define REASON0_CPURST 0x40
196 #define REASON0_BPRST 0x20
197 #define REASON0_COPRST 0x10
198 #define REASON0_SWCRST 0x08
199 #define REASON0_WDRST 0x04
200 #define REASON0_KBRST 0x02
201 #define REASON0_POWUP 0x01
203 (REASON0_POWUP | REASON0_COPRST | REASON0_KBRST |\
204 REASON0_BPRST | REASON0_SWURST | REASON0_WDRST)
205 #define CORE_RESET ((REASON1_CPUWD << 8) | REASON0_SWCRST)
207 bool qrio_reason_unitrst(void)
210 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
212 reason = in_be16(qrio_base + REASON1_OFF);
214 return (reason & UNIT_RESET) > 0;
217 #define RSTCFG_OFF 0x11
219 void qrio_uprstreq(u8 mode)
222 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
224 rstcfg = in_8(qrio_base + RSTCFG_OFF);
226 if (mode & UPREQ_CORE_RST)
227 rstcfg |= UPREQ_CORE_RST;
229 rstcfg &= ~UPREQ_CORE_RST;
231 out_8(qrio_base + RSTCFG_OFF, rstcfg);
234 /* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
235 * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
236 * For I2C only the low state is activly driven and high state is pulled-up
237 * by a resistor. Therefore the deblock GPIOs are used
238 * -> as an active output to drive a low state
239 * -> as an open-drain input to have a pulled-up high state
242 /* By default deblock GPIOs are floating */
243 void i2c_deblock_gpio_cfg(void)
245 /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
246 qrio_gpio_direction_input(KM_I2C_DEBLOCK_PORT,
248 qrio_gpio_direction_input(KM_I2C_DEBLOCK_PORT,
251 qrio_set_gpio(KM_I2C_DEBLOCK_PORT,
252 KM_I2C_DEBLOCK_SCL, 0);
253 qrio_set_gpio(KM_I2C_DEBLOCK_PORT,
254 KM_I2C_DEBLOCK_SDA, 0);
257 void set_sda(int state)
259 qrio_set_opendrain_gpio(KM_I2C_DEBLOCK_PORT,
260 KM_I2C_DEBLOCK_SDA, state);
263 void set_scl(int state)
265 qrio_set_opendrain_gpio(KM_I2C_DEBLOCK_PORT,
266 KM_I2C_DEBLOCK_SCL, state);
271 return qrio_get_gpio(KM_I2C_DEBLOCK_PORT,
277 return qrio_get_gpio(KM_I2C_DEBLOCK_PORT,