1 // SPDX-License-Identifier: GPL-2.0+
3 * K+P iMX6Q KP_IMX6Q_TPC board configuration
5 * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-ddr.h>
15 #include <asm/arch/sys_proto.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 static void ccgr_init(void)
24 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
26 writel(0x00C03F3F, &ccm->CCGR0);
27 writel(0x0030FC03, &ccm->CCGR1);
28 writel(0x0FFFC000, &ccm->CCGR2);
29 writel(0x3FF00000, &ccm->CCGR3);
30 writel(0x00FFF300, &ccm->CCGR4);
31 writel(0x0F0000C3, &ccm->CCGR5);
32 writel(0x000003FF, &ccm->CCGR6);
36 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
37 .dram_sdclk_0 = 0x00000030,
38 .dram_sdclk_1 = 0x00000030,
39 .dram_cas = 0x00000030,
40 .dram_ras = 0x00000030,
41 .dram_reset = 0x00000030,
42 .dram_sdcke0 = 0x00003000,
43 .dram_sdcke1 = 0x00003000,
44 .dram_sdba2 = 0x00000000,
45 .dram_sdodt0 = 0x00000030,
46 .dram_sdodt1 = 0x00000030,
48 .dram_sdqs0 = 0x00000018,
49 .dram_sdqs1 = 0x00000018,
50 .dram_sdqs2 = 0x00000018,
51 .dram_sdqs3 = 0x00000018,
52 .dram_sdqs4 = 0x00000018,
53 .dram_sdqs5 = 0x00000018,
54 .dram_sdqs6 = 0x00000018,
55 .dram_sdqs7 = 0x00000018,
57 .dram_dqm0 = 0x00000018,
58 .dram_dqm1 = 0x00000018,
59 .dram_dqm2 = 0x00000018,
60 .dram_dqm3 = 0x00000018,
61 .dram_dqm4 = 0x00000018,
62 .dram_dqm5 = 0x00000018,
63 .dram_dqm6 = 0x00000018,
64 .dram_dqm7 = 0x00000018,
67 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
68 .grp_ddr_type = 0x000c0000,
69 .grp_ddrmode_ctl = 0x00020000,
70 .grp_ddrpke = 0x00000000,
71 .grp_addds = 0x00000030,
72 .grp_ctlds = 0x00000030,
73 .grp_ddrmode = 0x00020000,
74 .grp_b0ds = 0x00000018,
75 .grp_b1ds = 0x00000018,
76 .grp_b2ds = 0x00000018,
77 .grp_b3ds = 0x00000018,
78 .grp_b4ds = 0x00000018,
79 .grp_b5ds = 0x00000018,
80 .grp_b6ds = 0x00000018,
81 .grp_b7ds = 0x00000018,
84 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
85 .p0_mpwldectrl0 = 0x001F001F,
86 .p0_mpwldectrl1 = 0x001F001F,
87 .p1_mpwldectrl0 = 0x001F001F,
88 .p1_mpwldectrl1 = 0x001F001F,
89 .p0_mpdgctrl0 = 0x43270338,
90 .p0_mpdgctrl1 = 0x03200314,
91 .p1_mpdgctrl0 = 0x431A032F,
92 .p1_mpdgctrl1 = 0x03200263,
93 .p0_mprddlctl = 0x4B434748,
94 .p1_mprddlctl = 0x4445404C,
95 .p0_mpwrdlctl = 0x38444542,
96 .p1_mpwrdlctl = 0x4935493A,
99 /* MT41K256M16 (4Gb density) */
100 static const struct mx6_ddr3_cfg mt41k256m16 = {
113 #ifdef CONFIG_MX6_DDRCAL
114 static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
116 struct mx6_mmdc_calibration calibration = {0};
118 mmdc_read_calibration(sysinfo, &calibration);
120 debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
121 debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
122 debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
123 debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
124 debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
125 debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
126 debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
127 debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
128 debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
129 debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
130 debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
131 debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
134 static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
138 /* Perform DDR DRAM calibration */
140 ret = mmdc_do_write_level_calibration(sysinfo);
142 printf("DDR: Write level calibration error [%d]\n", ret);
146 ret = mmdc_do_dqs_calibration(sysinfo);
148 printf("DDR: DQS calibration error [%d]\n", ret);
152 spl_dram_print_cal(sysinfo);
154 #endif /* CONFIG_MX6_DDRCAL */
156 static void spl_dram_init(void)
158 struct mx6_ddr_sysinfo sysinfo = {
159 /* width of data bus:0=16,1=32,2=64 */
161 /* config for full 4GB range so that get_mem_size() works */
162 .cs_density = 32, /* 32Gb per CS */
163 /* single chip select */
166 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
167 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
168 .walat = 1, /* Write additional latency */
169 .ralat = 5, /* Read additional latency */
170 .mif3_mode = 3, /* Command prediction working mode */
171 .bi_on = 1, /* Bank interleaving enabled */
172 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
173 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
174 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
175 .ddr_type = DDR_TYPE_DDR3,
176 .refsel = 1, /* Refresh cycles at 32KHz */
177 .refr = 7, /* 8 refresh commands per refresh cycle */
180 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
181 mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
183 #ifdef CONFIG_MX6_DDRCAL
184 spl_dram_perform_cal(&sysinfo);
188 void board_boot_order(u32 *spl_boot_list)
190 u32 boot_device = spl_boot_device();
191 u32 reg = imx6_src_get_boot_mode();
193 reg = (reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
195 debug("%s: boot device: 0x%x (0x4 SD, 0x6 eMMC)\n", __func__, reg);
196 if (boot_device == BOOT_DEVICE_MMC1)
197 if (reg == IMX6_BMODE_MMC || reg == IMX6_BMODE_EMMC)
198 boot_device = BOOT_DEVICE_MMC2;
200 spl_boot_list[0] = boot_device;
202 * Below boot device is a 'fallback' - it shall always be possible to
205 spl_boot_list[1] = BOOT_DEVICE_MMC1;
208 void board_init_f(ulong dummy)
210 /* setup AIPS and disable watchdog */
219 /* Early - pre reloc - driver model setup */
222 /* UART clocks enabled and gd valid - init serial console */
223 preloader_console_init();
225 /* DDR initialization */
229 memset(__bss_start, 0, __bss_end - __bss_start);