board/isee/igep00x0/igep00x0.c

   1 /*
   2  * (C) Copyright 2010
   3  * ISEE 2007 SL, <www.iseebcn.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <status_led.h>
   9 #include <dm.h>
  10 #include <ns16550.h>
  11 #include <twl4030.h>
  12 #include <netdev.h>
  13 #include <spl.h>
  14 #include <asm/gpio.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/mem.h>
  17 #include <asm/arch/mmc_host_def.h>
  18 #include <asm/arch/mux.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/mach-types.h>
  21 #include <linux/mtd/mtd.h>
  22 #include <linux/mtd/nand.h>
  23 #include <linux/mtd/nand.h>
  24 #include <linux/mtd/onenand.h>
  25 #include <jffs2/load_kernel.h>
  26 #include <mtd_node.h>
  27 #include <fdt_support.h>
  28 #include "igep00x0.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 static const struct ns16550_platdata igep_serial = {
  33         .base = OMAP34XX_UART3,
  34         .reg_shift = 2,
  35         .clock = V_NS16550_CLK
  36 };
  37
  38 U_BOOT_DEVICE(igep_uart) = {
  39         "ns16550_serial",
  40         &igep_serial
  41 };
  42
  43 /*
  44  * Routine: board_init
  45  * Description: Early hardware init.
  46  */
  47 int board_init(void)
  48 {
  49         int loops = 100;
  50
  51         /* find out flash memory type, assume NAND first */
  52         gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  53         gpmc_init();
  54
  55         /* Issue a RESET and then READID */
  56         writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
  57         writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
  58         while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
  59                                                 != NAND_STATUS_READY) {
  60                 udelay(1);
  61                 if (--loops == 0) {
  62                         gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
  63                         gpmc_init();    /* reinitialize for OneNAND */
  64                         break;
  65                 }
  66         }
  67
  68         /* boot param addr */
  69         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  70
  71 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
  72         status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
  73 #endif
  74
  75         return 0;
  76 }
  77
  78 #ifdef CONFIG_SPL_BUILD
  79 /*
  80  * Routine: get_board_mem_timings
  81  * Description: If we use SPL then there is no x-loader nor config header
  82  * so we have to setup the DDR timings ourself on both banks.
  83  */
  84 void get_board_mem_timings(struct board_sdrc_timings *timings)
  85 {
  86         int mfr, id, err = identify_nand_chip(&mfr, &id);
  87
  88         timings->mr = MICRON_V_MR_165;
  89         if (!err) {
  90                 switch (mfr) {
  91                 case NAND_MFR_HYNIX:
  92                         timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
  93                         timings->ctrla = HYNIX_V_ACTIMA_200;
  94                         timings->ctrlb = HYNIX_V_ACTIMB_200;
  95                         break;
  96                 case NAND_MFR_MICRON:
  97                         timings->mcfg = MICRON_V_MCFG_200(256 << 20);
  98                         timings->ctrla = MICRON_V_ACTIMA_200;
  99                         timings->ctrlb = MICRON_V_ACTIMB_200;
 100                         break;
 101                 default:
 102                         /* Should not happen... */
 103                         break;
 104                 }
 105                 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 106                 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
 107         } else {
 108                 if (get_cpu_family() == CPU_OMAP34XX) {
 109                         timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
 110                         timings->ctrla = NUMONYX_V_ACTIMA_165;
 111                         timings->ctrlb = NUMONYX_V_ACTIMB_165;
 112                         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 113                 } else {
 114                         timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
 115                         timings->ctrla = NUMONYX_V_ACTIMA_200;
 116                         timings->ctrlb = NUMONYX_V_ACTIMB_200;
 117                         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 118                 }
 119                 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
 120         }
 121 }
 122
 123 #ifdef CONFIG_SPL_OS_BOOT
 124 int spl_start_uboot(void)
 125 {
 126         /* break into full u-boot on 'c' */
 127         if (serial_tstc() && serial_getc() == 'c')
 128                 return 1;
 129
 130         return 0;
 131 }
 132 #endif
 133 #endif
 134
 135 int onenand_board_init(struct mtd_info *mtd)
 136 {
 137         if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
 138                 struct onenand_chip *this = mtd->priv;
 139                 this->base = (void *)CONFIG_SYS_ONENAND_BASE;
 140                 return 0;
 141         }
 142         return 1;
 143 }
 144
 145 #if defined(CONFIG_CMD_NET)
 146 static void reset_net_chip(int gpio)
 147 {
 148         if (!gpio_request(gpio, "eth nrst")) {
 149                 gpio_direction_output(gpio, 1);
 150                 udelay(1);
 151                 gpio_set_value(gpio, 0);
 152                 udelay(40);
 153                 gpio_set_value(gpio, 1);
 154                 mdelay(10);
 155         }
 156 }
 157
 158 /*
 159  * Routine: setup_net_chip
 160  * Description: Setting up the configuration GPMC registers specific to the
 161  *              Ethernet hardware.
 162  */
 163 static void setup_net_chip(void)
 164 {
 165         struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 166         static const u32 gpmc_lan_config[] = {
 167                 NET_LAN9221_GPMC_CONFIG1,
 168                 NET_LAN9221_GPMC_CONFIG2,
 169                 NET_LAN9221_GPMC_CONFIG3,
 170                 NET_LAN9221_GPMC_CONFIG4,
 171                 NET_LAN9221_GPMC_CONFIG5,
 172                 NET_LAN9221_GPMC_CONFIG6,
 173         };
 174
 175         enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
 176                         CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
 177
 178         /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 179         writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
 180         /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
 181         writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
 182         /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
 183         writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
 184                 &ctrl_base->gpmc_nadv_ale);
 185
 186         reset_net_chip(64);
 187 }
 188
 189 int board_eth_init(bd_t *bis)
 190 {
 191 #ifdef CONFIG_SMC911X
 192         return smc911x_initialize(0, CONFIG_SMC911X_BASE);
 193 #else
 194         return 0;
 195 #endif
 196 }
 197 #else
 198 static inline void setup_net_chip(void) {}
 199 #endif
 200
 201 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 202 int board_mmc_init(bd_t *bis)
 203 {
 204         return omap_mmc_init(0, 0, 0, -1, -1);
 205 }
 206 #endif
 207
 208 #if defined(CONFIG_GENERIC_MMC)
 209 void board_mmc_power_init(void)
 210 {
 211         twl4030_power_mmc_init(0);
 212 }
 213 #endif
 214
 215 #ifdef CONFIG_OF_BOARD_SETUP
 216 int ft_board_setup(void *blob, bd_t *bd)
 217 {
 218 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 219         static struct node_info nodes[] = {
 220                 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
 221                 { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, },
 222         };
 223
 224         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 225 #endif
 226         return 0;
 227 }
 228 #endif
 229
 230 void set_fdt(void)
 231 {
 232         switch (gd->bd->bi_arch_number) {
 233         case MACH_TYPE_IGEP0020:
 234                 setenv("fdtfile", "omap3-igep0020.dtb");
 235                 break;
 236         case MACH_TYPE_IGEP0030:
 237                 setenv("fdtfile", "omap3-igep0030.dtb");
 238                 break;
 239         }
 240 }
 241
 242 /*
 243  * Routine: misc_init_r
 244  * Description: Configure board specific parts
 245  */
 246 int misc_init_r(void)
 247 {
 248         twl4030_power_init();
 249
 250         setup_net_chip();
 251
 252         omap_die_id_display();
 253
 254         set_fdt();
 255
 256         return 0;
 257 }
 258
 259 void board_mtdparts_default(const char **mtdids, const char **mtdparts)
 260 {
 261         struct mtd_info *mtd = get_mtd_device(NULL, 0);
 262         if (mtd) {
 263                 static char ids[24];
 264                 static char parts[48];
 265                 const char *linux_name = "omap2-nand";
 266                 if (strncmp(mtd->name, "onenand0", 8) == 0)
 267                         linux_name = "omap2-onenand";
 268                 snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
 269                 snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
 270                          linux_name, 4 * mtd->erasesize >> 10);
 271                 *mtdids = ids;
 272                 *mtdparts = parts;
 273         }
 274 }
 275
 276 /*
 277  * Routine: set_muxconf_regs
 278  * Description: Setting up the configuration Mux registers specific to the
 279  *              hardware. Many pins need to be moved from protect to primary
 280  *              mode.
 281  */
 282 void set_muxconf_regs(void)
 283 {
 284         MUX_DEFAULT();
 285
 286 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
 287         MUX_IGEP0020();
 288 #endif
 289
 290 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
 291         MUX_IGEP0030();
 292 #endif
 293 }