board/isee/igep00x0/igep00x0.c

   1 /*
   2  * (C) Copyright 2010
   3  * ISEE 2007 SL, <www.iseebcn.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <status_led.h>
   9 #include <dm.h>
  10 #include <ns16550.h>
  11 #include <twl4030.h>
  12 #include <netdev.h>
  13 #include <asm/gpio.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/mem.h>
  16 #include <asm/arch/mmc_host_def.h>
  17 #include <asm/arch/mux.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/mach-types.h>
  20 #include "igep00x0.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 const omap3_sysinfo sysinfo = {
  25         DDR_STACKED,
  26 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
  27         "IGEPv2",
  28 #endif
  29 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
  30         "IGEP COM MODULE/ELECTRON",
  31 #endif
  32 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
  33         "IGEP COM PROTON",
  34 #endif
  35 #if defined(CONFIG_ENV_IS_IN_ONENAND)
  36         "ONENAND",
  37 #else
  38         "NAND",
  39 #endif
  40 };
  41
  42 static const struct ns16550_platdata igep_serial = {
  43         .base = OMAP34XX_UART3,
  44         .reg_shift = 2,
  45         .clock = V_NS16550_CLK
  46 };
  47
  48 U_BOOT_DEVICE(igep_uart) = {
  49         "ns16550_serial",
  50         &igep_serial
  51 };
  52
  53 /*
  54  * Routine: board_init
  55  * Description: Early hardware init.
  56  */
  57 int board_init(void)
  58 {
  59         gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  60         /* boot param addr */
  61         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  62
  63 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
  64         status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
  65 #endif
  66
  67         return 0;
  68 }
  69
  70 #ifdef CONFIG_SPL_BUILD
  71 /*
  72  * Routine: get_board_mem_timings
  73  * Description: If we use SPL then there is no x-loader nor config header
  74  * so we have to setup the DDR timings ourself on both banks.
  75  */
  76 void get_board_mem_timings(struct board_sdrc_timings *timings)
  77 {
  78         timings->mr = MICRON_V_MR_165;
  79 #ifdef CONFIG_BOOT_NAND
  80         timings->mcfg = MICRON_V_MCFG_200(256 << 20);
  81         timings->ctrla = MICRON_V_ACTIMA_200;
  82         timings->ctrlb = MICRON_V_ACTIMB_200;
  83         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  84 #else
  85         if (get_cpu_family() == CPU_OMAP34XX) {
  86                 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
  87                 timings->ctrla = NUMONYX_V_ACTIMA_165;
  88                 timings->ctrlb = NUMONYX_V_ACTIMB_165;
  89                 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  90
  91         } else {
  92                 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
  93                 timings->ctrla = NUMONYX_V_ACTIMA_200;
  94                 timings->ctrlb = NUMONYX_V_ACTIMB_200;
  95                 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  96         }
  97 #endif
  98 }
  99 #endif
 100
 101 #if defined(CONFIG_CMD_NET)
 102 static void reset_net_chip(int gpio)
 103 {
 104         if (!gpio_request(gpio, "eth nrst")) {
 105                 gpio_direction_output(gpio, 1);
 106                 udelay(1);
 107                 gpio_set_value(gpio, 0);
 108                 udelay(40);
 109                 gpio_set_value(gpio, 1);
 110                 mdelay(10);
 111         }
 112 }
 113
 114 /*
 115  * Routine: setup_net_chip
 116  * Description: Setting up the configuration GPMC registers specific to the
 117  *              Ethernet hardware.
 118  */
 119 static void setup_net_chip(void)
 120 {
 121         struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 122         static const u32 gpmc_lan_config[] = {
 123                 NET_LAN9221_GPMC_CONFIG1,
 124                 NET_LAN9221_GPMC_CONFIG2,
 125                 NET_LAN9221_GPMC_CONFIG3,
 126                 NET_LAN9221_GPMC_CONFIG4,
 127                 NET_LAN9221_GPMC_CONFIG5,
 128                 NET_LAN9221_GPMC_CONFIG6,
 129         };
 130
 131         enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
 132                         CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
 133
 134         /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 135         writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
 136         /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
 137         writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
 138         /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
 139         writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
 140                 &ctrl_base->gpmc_nadv_ale);
 141
 142         reset_net_chip(64);
 143 }
 144
 145 int board_eth_init(bd_t *bis)
 146 {
 147 #ifdef CONFIG_SMC911X
 148         return smc911x_initialize(0, CONFIG_SMC911X_BASE);
 149 #else
 150         return 0;
 151 #endif
 152 }
 153 #else
 154 static inline void setup_net_chip(void) {}
 155 #endif
 156
 157 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 158 int board_mmc_init(bd_t *bis)
 159 {
 160         return omap_mmc_init(0, 0, 0, -1, -1);
 161 }
 162 #endif
 163
 164 #if defined(CONFIG_GENERIC_MMC)
 165 void board_mmc_power_init(void)
 166 {
 167         twl4030_power_mmc_init(0);
 168 }
 169 #endif
 170
 171 void set_fdt(void)
 172 {
 173         switch (gd->bd->bi_arch_number) {
 174         case MACH_TYPE_IGEP0020:
 175                 setenv("fdtfile", "omap3-igep0020.dtb");
 176                 break;
 177         case MACH_TYPE_IGEP0030:
 178                 setenv("fdtfile", "omap3-igep0030.dtb");
 179                 break;
 180         }
 181 }
 182
 183 /*
 184  * Routine: misc_init_r
 185  * Description: Configure board specific parts
 186  */
 187 int misc_init_r(void)
 188 {
 189         twl4030_power_init();
 190
 191         setup_net_chip();
 192
 193         omap_die_id_display();
 194
 195         set_fdt();
 196
 197         return 0;
 198 }
 199
 200 /*
 201  * Routine: set_muxconf_regs
 202  * Description: Setting up the configuration Mux registers specific to the
 203  *              hardware. Many pins need to be moved from protect to primary
 204  *              mode.
 205  */
 206 void set_muxconf_regs(void)
 207 {
 208         MUX_DEFAULT();
 209
 210 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
 211         MUX_IGEP0020();
 212 #endif
 213
 214 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
 215         MUX_IGEP0030();
 216 #endif
 217 }