board/isee/igep00x0/igep00x0.c

   1 /*
   2  * (C) Copyright 2010
   3  * ISEE 2007 SL, <www.iseebcn.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <status_led.h>
   9 #include <dm.h>
  10 #include <ns16550.h>
  11 #include <twl4030.h>
  12 #include <netdev.h>
  13 #include <spl.h>
  14 #include <asm/gpio.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/mem.h>
  17 #include <asm/arch/mmc_host_def.h>
  18 #include <asm/arch/mux.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/mach-types.h>
  21 #include <linux/mtd/mtd.h>
  22 #include <linux/mtd/nand.h>
  23 #include <linux/mtd/nand.h>
  24 #include <linux/mtd/onenand.h>
  25 #include <jffs2/load_kernel.h>
  26 #include "igep00x0.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 static const struct ns16550_platdata igep_serial = {
  31         .base = OMAP34XX_UART3,
  32         .reg_shift = 2,
  33         .clock = V_NS16550_CLK
  34 };
  35
  36 U_BOOT_DEVICE(igep_uart) = {
  37         "ns16550_serial",
  38         &igep_serial
  39 };
  40
  41 /*
  42  * Routine: board_init
  43  * Description: Early hardware init.
  44  */
  45 int board_init(void)
  46 {
  47         int loops = 100;
  48
  49         /* find out flash memory type, assume NAND first */
  50         gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  51         gpmc_init();
  52
  53         /* Issue a RESET and then READID */
  54         writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
  55         writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
  56         while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
  57                                                 != NAND_STATUS_READY) {
  58                 udelay(1);
  59                 if (--loops == 0) {
  60                         gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
  61                         gpmc_init();    /* reinitialize for OneNAND */
  62                         break;
  63                 }
  64         }
  65
  66         /* boot param addr */
  67         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  68
  69 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
  70         status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
  71 #endif
  72
  73         return 0;
  74 }
  75
  76 #ifdef CONFIG_SPL_BUILD
  77 /*
  78  * Routine: get_board_mem_timings
  79  * Description: If we use SPL then there is no x-loader nor config header
  80  * so we have to setup the DDR timings ourself on both banks.
  81  */
  82 void get_board_mem_timings(struct board_sdrc_timings *timings)
  83 {
  84         int mfr, id, err = identify_nand_chip(&mfr, &id);
  85
  86         timings->mr = MICRON_V_MR_165;
  87         if (!err && mfr == NAND_MFR_MICRON) {
  88                 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
  89                 timings->ctrla = MICRON_V_ACTIMA_200;
  90                 timings->ctrlb = MICRON_V_ACTIMB_200;
  91                 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  92                 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  93         } else {
  94                 if (get_cpu_family() == CPU_OMAP34XX) {
  95                         timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
  96                         timings->ctrla = NUMONYX_V_ACTIMA_165;
  97                         timings->ctrlb = NUMONYX_V_ACTIMB_165;
  98                         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  99                 } else {
 100                         timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
 101                         timings->ctrla = NUMONYX_V_ACTIMA_200;
 102                         timings->ctrlb = NUMONYX_V_ACTIMB_200;
 103                         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 104                 }
 105                 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
 106         }
 107 }
 108
 109 #ifdef CONFIG_SPL_OS_BOOT
 110 int spl_start_uboot(void)
 111 {
 112         /* break into full u-boot on 'c' */
 113         if (serial_tstc() && serial_getc() == 'c')
 114                 return 1;
 115
 116         return 0;
 117 }
 118 #endif
 119 #endif
 120
 121 int onenand_board_init(struct mtd_info *mtd)
 122 {
 123         if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
 124                 struct onenand_chip *this = mtd->priv;
 125                 this->base = (void *)CONFIG_SYS_ONENAND_BASE;
 126                 return 0;
 127         }
 128         return 1;
 129 }
 130
 131 #if defined(CONFIG_CMD_NET)
 132 static void reset_net_chip(int gpio)
 133 {
 134         if (!gpio_request(gpio, "eth nrst")) {
 135                 gpio_direction_output(gpio, 1);
 136                 udelay(1);
 137                 gpio_set_value(gpio, 0);
 138                 udelay(40);
 139                 gpio_set_value(gpio, 1);
 140                 mdelay(10);
 141         }
 142 }
 143
 144 /*
 145  * Routine: setup_net_chip
 146  * Description: Setting up the configuration GPMC registers specific to the
 147  *              Ethernet hardware.
 148  */
 149 static void setup_net_chip(void)
 150 {
 151         struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 152         static const u32 gpmc_lan_config[] = {
 153                 NET_LAN9221_GPMC_CONFIG1,
 154                 NET_LAN9221_GPMC_CONFIG2,
 155                 NET_LAN9221_GPMC_CONFIG3,
 156                 NET_LAN9221_GPMC_CONFIG4,
 157                 NET_LAN9221_GPMC_CONFIG5,
 158                 NET_LAN9221_GPMC_CONFIG6,
 159         };
 160
 161         enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
 162                         CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
 163
 164         /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 165         writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
 166         /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
 167         writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
 168         /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
 169         writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
 170                 &ctrl_base->gpmc_nadv_ale);
 171
 172         reset_net_chip(64);
 173 }
 174
 175 int board_eth_init(bd_t *bis)
 176 {
 177 #ifdef CONFIG_SMC911X
 178         return smc911x_initialize(0, CONFIG_SMC911X_BASE);
 179 #else
 180         return 0;
 181 #endif
 182 }
 183 #else
 184 static inline void setup_net_chip(void) {}
 185 #endif
 186
 187 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 188 int board_mmc_init(bd_t *bis)
 189 {
 190         return omap_mmc_init(0, 0, 0, -1, -1);
 191 }
 192 #endif
 193
 194 #if defined(CONFIG_GENERIC_MMC)
 195 void board_mmc_power_init(void)
 196 {
 197         twl4030_power_mmc_init(0);
 198 }
 199 #endif
 200
 201 void set_fdt(void)
 202 {
 203         switch (gd->bd->bi_arch_number) {
 204         case MACH_TYPE_IGEP0020:
 205                 setenv("fdtfile", "omap3-igep0020.dtb");
 206                 break;
 207         case MACH_TYPE_IGEP0030:
 208                 setenv("fdtfile", "omap3-igep0030.dtb");
 209                 break;
 210         }
 211 }
 212
 213 /*
 214  * Routine: misc_init_r
 215  * Description: Configure board specific parts
 216  */
 217 int misc_init_r(void)
 218 {
 219         twl4030_power_init();
 220
 221         setup_net_chip();
 222
 223         omap_die_id_display();
 224
 225         set_fdt();
 226
 227         return 0;
 228 }
 229
 230 void board_mtdparts_default(const char **mtdids, const char **mtdparts)
 231 {
 232         struct mtd_info *mtd = get_mtd_device(NULL, 0);
 233         if (mtd) {
 234                 static char ids[24];
 235                 static char parts[48];
 236                 const char *linux_name = "omap2-nand";
 237                 if (strncmp(mtd->name, "onenand0", 8) == 0)
 238                         linux_name = "omap2-onenand";
 239                 snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
 240                 snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
 241                          linux_name, 4 * mtd->erasesize >> 10);
 242                 *mtdids = ids;
 243                 *mtdparts = parts;
 244         }
 245 }
 246
 247 /*
 248  * Routine: set_muxconf_regs
 249  * Description: Setting up the configuration Mux registers specific to the
 250  *              hardware. Many pins need to be moved from protect to primary
 251  *              mode.
 252  */
 253 void set_muxconf_regs(void)
 254 {
 255         MUX_DEFAULT();
 256
 257 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
 258         MUX_IGEP0020();
 259 #endif
 260
 261 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
 262         MUX_IGEP0030();
 263 #endif
 264 }