board/isee/igep00x0/igep00x0.c

   1 /*
   2  * (C) Copyright 2010
   3  * ISEE 2007 SL, <www.iseebcn.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <status_led.h>
   9 #include <dm.h>
  10 #include <ns16550.h>
  11 #include <twl4030.h>
  12 #include <netdev.h>
  13 #include <asm/gpio.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/mem.h>
  16 #include <asm/arch/mmc_host_def.h>
  17 #include <asm/arch/mux.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/mach-types.h>
  20 #include <linux/mtd/mtd.h>
  21 #include <linux/mtd/nand.h>
  22 #include <linux/mtd/nand.h>
  23 #include <linux/mtd/onenand.h>
  24 #include <jffs2/load_kernel.h>
  25 #include "igep00x0.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 const omap3_sysinfo sysinfo = {
  30         DDR_STACKED,
  31 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
  32         "IGEPv2",
  33 #endif
  34 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
  35         "IGEP COM MODULE/ELECTRON",
  36 #endif
  37 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
  38         "IGEP COM PROTON",
  39 #endif
  40 #if defined(CONFIG_ENV_IS_IN_ONENAND)
  41         "ONENAND",
  42 #else
  43         "NAND",
  44 #endif
  45 };
  46
  47 static const struct ns16550_platdata igep_serial = {
  48         .base = OMAP34XX_UART3,
  49         .reg_shift = 2,
  50         .clock = V_NS16550_CLK
  51 };
  52
  53 U_BOOT_DEVICE(igep_uart) = {
  54         "ns16550_serial",
  55         &igep_serial
  56 };
  57
  58 /*
  59  * Routine: board_init
  60  * Description: Early hardware init.
  61  */
  62 int board_init(void)
  63 {
  64         int loops = 100;
  65
  66         /* find out flash memory type, assume NAND first */
  67         gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  68         gpmc_init();
  69
  70         /* Issue a RESET and then READID */
  71         writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
  72         writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
  73         while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
  74                                                 != NAND_STATUS_READY) {
  75                 udelay(1);
  76                 if (--loops == 0) {
  77                         gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
  78                         gpmc_init();    /* reinitialize for OneNAND */
  79                         break;
  80                 }
  81         }
  82
  83         /* boot param addr */
  84         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  85
  86 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
  87         status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
  88 #endif
  89
  90         return 0;
  91 }
  92
  93 #ifdef CONFIG_SPL_BUILD
  94 /*
  95  * Routine: get_board_mem_timings
  96  * Description: If we use SPL then there is no x-loader nor config header
  97  * so we have to setup the DDR timings ourself on both banks.
  98  */
  99 void get_board_mem_timings(struct board_sdrc_timings *timings)
 100 {
 101         int mfr, id, err = identify_nand_chip(&mfr, &id);
 102
 103         timings->mr = MICRON_V_MR_165;
 104         if (!err && mfr == NAND_MFR_MICRON) {
 105                 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
 106                 timings->ctrla = MICRON_V_ACTIMA_200;
 107                 timings->ctrlb = MICRON_V_ACTIMB_200;
 108                 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 109                 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
 110         } else {
 111                 if (get_cpu_family() == CPU_OMAP34XX) {
 112                         timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
 113                         timings->ctrla = NUMONYX_V_ACTIMA_165;
 114                         timings->ctrlb = NUMONYX_V_ACTIMB_165;
 115                         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 116                 } else {
 117                         timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
 118                         timings->ctrla = NUMONYX_V_ACTIMA_200;
 119                         timings->ctrlb = NUMONYX_V_ACTIMB_200;
 120                         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 121                 }
 122                 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
 123         }
 124 }
 125 #endif
 126
 127 int onenand_board_init(struct mtd_info *mtd)
 128 {
 129         if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
 130                 struct onenand_chip *this = mtd->priv;
 131                 this->base = (void *)CONFIG_SYS_ONENAND_BASE;
 132                 return 0;
 133         }
 134         return 1;
 135 }
 136
 137 #if defined(CONFIG_CMD_NET)
 138 static void reset_net_chip(int gpio)
 139 {
 140         if (!gpio_request(gpio, "eth nrst")) {
 141                 gpio_direction_output(gpio, 1);
 142                 udelay(1);
 143                 gpio_set_value(gpio, 0);
 144                 udelay(40);
 145                 gpio_set_value(gpio, 1);
 146                 mdelay(10);
 147         }
 148 }
 149
 150 /*
 151  * Routine: setup_net_chip
 152  * Description: Setting up the configuration GPMC registers specific to the
 153  *              Ethernet hardware.
 154  */
 155 static void setup_net_chip(void)
 156 {
 157         struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 158         static const u32 gpmc_lan_config[] = {
 159                 NET_LAN9221_GPMC_CONFIG1,
 160                 NET_LAN9221_GPMC_CONFIG2,
 161                 NET_LAN9221_GPMC_CONFIG3,
 162                 NET_LAN9221_GPMC_CONFIG4,
 163                 NET_LAN9221_GPMC_CONFIG5,
 164                 NET_LAN9221_GPMC_CONFIG6,
 165         };
 166
 167         enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
 168                         CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
 169
 170         /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 171         writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
 172         /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
 173         writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
 174         /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
 175         writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
 176                 &ctrl_base->gpmc_nadv_ale);
 177
 178         reset_net_chip(64);
 179 }
 180
 181 int board_eth_init(bd_t *bis)
 182 {
 183 #ifdef CONFIG_SMC911X
 184         return smc911x_initialize(0, CONFIG_SMC911X_BASE);
 185 #else
 186         return 0;
 187 #endif
 188 }
 189 #else
 190 static inline void setup_net_chip(void) {}
 191 #endif
 192
 193 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 194 int board_mmc_init(bd_t *bis)
 195 {
 196         return omap_mmc_init(0, 0, 0, -1, -1);
 197 }
 198 #endif
 199
 200 #if defined(CONFIG_GENERIC_MMC)
 201 void board_mmc_power_init(void)
 202 {
 203         twl4030_power_mmc_init(0);
 204 }
 205 #endif
 206
 207 void set_fdt(void)
 208 {
 209         switch (gd->bd->bi_arch_number) {
 210         case MACH_TYPE_IGEP0020:
 211                 setenv("fdtfile", "omap3-igep0020.dtb");
 212                 break;
 213         case MACH_TYPE_IGEP0030:
 214                 setenv("fdtfile", "omap3-igep0030.dtb");
 215                 break;
 216         }
 217 }
 218
 219 /*
 220  * Routine: misc_init_r
 221  * Description: Configure board specific parts
 222  */
 223 int misc_init_r(void)
 224 {
 225         twl4030_power_init();
 226
 227         setup_net_chip();
 228
 229         omap_die_id_display();
 230
 231         set_fdt();
 232
 233         return 0;
 234 }
 235
 236 void board_mtdparts_default(const char **mtdids, const char **mtdparts)
 237 {
 238         struct mtd_info *mtd = get_mtd_device(NULL, 0);
 239         if (mtd) {
 240                 static char ids[24];
 241                 static char parts[48];
 242                 const char *linux_name = "omap2-nand";
 243                 if (strncmp(mtd->name, "onenand0", 8) == 0)
 244                         linux_name = "omap2-onenand";
 245                 snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
 246                 snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
 247                          linux_name, 4 * mtd->erasesize >> 10);
 248                 *mtdids = ids;
 249                 *mtdparts = parts;
 250         }
 251 }
 252
 253 /*
 254  * Routine: set_muxconf_regs
 255  * Description: Setting up the configuration Mux registers specific to the
 256  *              hardware. Many pins need to be moved from protect to primary
 257  *              mode.
 258  */
 259 void set_muxconf_regs(void)
 260 {
 261         MUX_DEFAULT();
 262
 263 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
 264         MUX_IGEP0020();
 265 #endif
 266
 267 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
 268         MUX_IGEP0030();
 269 #endif
 270 }